
10-1038
Thermal Drift
Thermal drift is based on measurements at 25
o
C, at high
(T
H
) and low (T
L
) temperatures. Drift calculations are made
for the high (T
H
-25
o
C) and low (25
o
C-T
L
) ranges, and the
larger of the two values is given as a specification represent-
ing worst case drift.
Gain Drift, Offset Drift, Reference Drift and Total Bipolar Drift
are calculated in parts per million per
o
C as follows:
NOTE: FSR = Full Scale Output Voltage - Zero Scale Output
Voltage
FSR = FSR (T
H
) - FSR (25
o
C),
or FSR (25
o
C) - FSR (T
L
).
V
O
= Steady State response to any input code.
Total Bipolar Drift is the variation of output voltage with
temperature, in the bipolar mode of operation. It represents
the net effect of drift in Gain, Offset, Linearity and Reference
Voltage. Total Bipolar Drift values are calculated, based on
measurements as explained above. Gain and Offset need
not be calibrated to zero at 25
o
C. The specified limits for
TBD apply for any input code and for any power supply set-
ting within the specified operating range.
Accuracy
Linearity Error
(Short for “Integral Linearity Error.” Also,
sometimes called “Integral Nonlinearity” and “Nonlinearity”.)
The maximum deviation of the actual transfer characteristic
from an ideal straight line. The ideal line is positioned
according to end-point linearity for D/A converter products
from Intersil Corporation , i.e., the line is drawn between the
end-points of the actual transfer characteristic (codes 00...0
and 11...1).
Differential Linearity Error
The difference between one
LSB and the output voltage change corresponding to any
two consecutive codes. A Differential Nonlinearity of
±
1 LSB
or less guarantees monotonicity.
Monotonicity
The property of a D/A converter’s transfer
function which guarantees that the output derivative will not
change sign in response to a sequence of increasing (or
decreasing) input codes. That is, the only output response to
a code change is to remain constant, increase for Increasing
code, or decrease for decreasing code.
Total Error
The net output error resulting from all internal
effects (primarily non-ideal Gain, Offset, Linearity and
Reference Voltage). Supply voltages may be set to any
values within the specified operating range. Gain and offset
errors must be calibrated to zero at 25
o
C. Then the specified
limits for Total Error apply for any input code and for any
temperature within the specified operating range.
Power Supply Sensitivity
Power Supply Sensitivity is a measure of the change in gain
and offset of the D/A converter resulting from a change in
-V
S
, or +V
S
supplies. It is specified under DC conditions and
expressed as full scale range percent of change divided by
power supply percent change.
Glitch
A glitch on the output of a D/A converter is a transient spike
resulting from unequal internal ON-OFF switching times.
Worst case glitches usually occur at half-scale, i.e., the
major carry code transition from 011...1 to 100...0 or vice
versa. For example, if turn ON is greater than OFF for
011...1 to 100...0, an intermediate state of 000...0 exists,
such that, the output momentarily glitches toward zero out-
put. Matched switching times and fast switching will reduce
glitches considerably. (Measured as one half the Product of
duration and amplitude.)
Decoupling and Grounding
For best accuracy and high frequency performance, the
grounding and decoupling scheme shown in Figure 1 should
be used. Decoupling capacitors should be connected close
to the HI-DAC80V/HI-DAC85V (preferably to the device pins)
and should be tantalum or electrolytic bypassed with
ceramic types for best high frequency noise rejection.
GainDrift
C
-------------------------------
10
6
×
=
OffsetDrift
C
-------------------------------------
10
6
×
=
ReferenceDrift
V
°
C
(
)
REF
10
6
×
=
TotalBipolarDrift
V
--------------------------------
°
C
(
)
10
6
×
=
PSS
S
-------------------------------------------------------------------
-------------------------------------------------------------------
---------------------------------
=
18
19
20
15
-
+
-V
S
+V
S
0.01
μ
F
1
μ
F
14
21
22
0.01
μ
F
1
μ
F
24
16
FIGURE 1.
HI-DAC80V HI-DAC85V