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參數(shù)資料
| 型號： | HI2300JCQ |
| 廠商： | INTERSIL CORP |
| 元件分類： | ADC |
| 英文描述： | 8-Bit, 18 MSPS, Video A/D Converter with 3.3V Power Supply Operation |
| 中文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP32 |
| 封裝： | 7 X 7 MM, MQFP-32 |
| 文件頁數(shù)： | 7/8頁 |
| 文件大?。?/td> | 96K |
| 代理商： | HI2300JCQ |
4-1236
Typical Application Circuits
NOTE:
1. The clamp pulse is latched by the sampling clock of ADC, but that is not necessary for basic clamp operaiotn. However, slight small beat
may be generated as Vertical sag according to the relationship between the sampling frequency and the clamp pulse frequency. At such
time, the latch circuit is efective in this case.
FIGURE 1. WHEN CLAMP IS USED (SELF BIAS)
NOTES:
2. The relationship between the changes in CCP voltage (Pin 27) and in V
IN
voltage is positive phase.
3.
V
IN
/
V
CCP
= 3.0 (f
S
= 20 MSPS).
FIGURE 2. DIGITAL CLAMP (SELF BIAS)
8
7
6
5
4
3
2
1
16
15
14
13
12
11
10
9
25
26
27
28
29
30
31
32
CLOCK IN
10
μ
0.1
μ
+3.3V (DIGITAL)
CLAMP PULSE IN
VIDEO IN
V
REF
20K
LATCHCK
(NOTE 2)
Q
75
0.01
μ
10p
0.1
μ
GND (ANALOG)
GND (DIGITAL)
D0
D1
D2
D3
D4
D5
D6
D7
HC04
0.01
μ
+3.3V (ANALOG)
+3.3V
(ANALOG)
0.01
μ
OPEN
+
17
18
19
20
21
22
23
24
DAC,
PWM,
ETC.
CLAMP LEVEL
SETTING DATA
16
15
14
13
12
11
10
9
25
26
27
28
29
30
31
32
CLOCK IN
10
μ
0.1
μ
+3.3V (DIGITAL)
VIDEO IN
75
0.01
μ
10p
0.1
μ
GND (ANALOG)
GND (DIGITAL)
HC04
0.01
μ
+3.3V (ANALOG)
0.01
μ
OPEN
+
17
18
19
20
21
22
23
24
8
7
6
5
4
3
2
1
SUBTRACTER,
COMPARATOR,
ETC.
INFORMATION OTHER THAN
CLAMP INTERVAL IS AT
HIGH IMPEDANCE.
HI2300
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