參數(shù)資料
型號(hào)： HI1260
廠(chǎng)商： Intersil Corporation
英文描述： Triple 8-Bit, 35 MSPS, RGB, 3-Channel D/A Converter
中文描述： 三8位，35 MSPS的，的RGB，3通道D / A轉(zhuǎn)換
文件頁(yè)數(shù)： 9/13頁(yè)
文件大?。?/td> 166K
代理商： HI1260
10-9
Timing Diagram
FIGURE 6. GLITCH ENERGY TEST CIRCUIT
Test Circuits and Waveforms
(Continued)
OUT
8-BIT
COUNTER
(TTL OUTPUT)
D2
(MSB)
(LSB)
D8
D1 -D8
8 (R)
33
D1 -D8
8 (G)
D1 -D8
8 (B)
39 - 42
44 - 47
1 - 8
9 - 16
31
29
27
24
23
20
18
R
OUT
G
OUT
B
OUT
V
SET
V
+
-
33
μ
F
3K
CLK
HI1260
CLK
IN
19, 37, 43
DIGITAL RAMP WAVEFORM GENERATION
MCLK
f = 1 MSPS
TTL LEVEL
RECTANGULAR
WAVE
5ns TO 300ns
D1 TO D8
AGND
DGND
DV
CC
AV
CC
25
100
P
F
TIMING OF CLK AND DATA
D1
V
REF
t
1
t
12
t
2
t
3
t
34
t
4
V
TH
=
1.5V
V
TH
=
1.4V
t
X
t
Y
t
H
t
S
t
S
t
H
V
TH:
THRESHOLD LEVEL
100%
90%
10%
0%
100%
0%
10%
90%
t
f
t
r
CLK
DATA
D/A OUT
FIGURE 7.
At the time t = t
x
, the data of individual bits are
switched and thereafter, when the CLK becomes L
→
H at t = t
2
, the D/A OUT is varied synchronous with it.
That is, the D/A OUT is synchronous with the rise of
the CLK. (In this case, fetching of the data is carried
out at the fall of the CLK (at the time when t = T
12
).)
At the time t = T
Y
, the data of individual bits are
switched and thereafter, when the CLK becomes L
→
H at t = t
4
, the D/A OUT is synchronous with it. That
is, the D/A OUT is synchronous with the rise of the
CLK. (In this case, fetching of the data is carried out
at the fall of CLK (at the time when t = t
4
).)
t
PW1
t
PW0
HI1260
相關(guān)PDF資料
PDF描述
HI1260JCQ Triple 8-Bit, 35 MSPS, RGB, 3-Channel D/A Converter
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HI1276-EV 8-Bit, 500 MSPS, Flash A/D Converter
HI1276AIL 8-Bit, 500 MSPS, Flash A/D Converter
相關(guān)代理商/技術(shù)參數(shù)
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HI1276 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:8-Bit, 500 MSPS, Flash A/D Converter
HI1276AIL 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:8-Bit, 500 MSPS, Flash A/D Converter
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