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參數(shù)資料
| 型號： | HI1175JCB |
| 廠商： | Intersil |
| 文件頁數(shù)： | 8/13頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 8-BIT FLASH 20MSPS 24SOIC |
| 標準包裝： | 300 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 20M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 60mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SOIC W |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個單端，單極 |
4
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V
Reference Voltage, VRT, VRB . . . . . . . . . . . . . . . . . . . . VDD to VSS
Analog Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . VDD to VSS
Digital Input Voltage, CLK . . . . . . . . . . . . . . . . . . . . . . . VDD to VSS
Digital Output Voltage, VOH, VOL . . . . . . . . . . . . . . . . . VDD to VSS
Operating Conditions (Note 1)
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -40
oC to 85oC
Supply Voltage
AVDD, AVSS, DVDD, DVSS. . . . . . . . . . . . . . . . +4.75V to +5.25V
|DGND-AGND|. . . . . . . . . . . . . . . . . . . . . . . . . . . . 0mV to 100mV
Reference Input Voltage
VRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V and Above
VRT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8V and Below
Analog Input Range, VIN . . . . . . . VRB to VRT (1.8VP-P to 2.8VP-P)
Clock Pulse Width
tPW1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns (Min)
tPW0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns (Min)
Thermal Resistance (Typical, Note 1)
θ
JA (
oC/W)
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
98
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range, TSTG. . . . . -65
oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
fC = 20 MSPS, VDD = +5V, VRB = 0.5V, VRT = 2.5V, TA = 25
oC (Note 1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SYSTEM PERFORMANCE
Offset Voltage
-
---
EOT
-60
-35
-10
mV
EOB
0+15
+45
mV
Integral Non-Linearity, INL
fC = 20 MSPS, VIN = 0.6V to 2.6V
-
±0.5
±1.3
LSB
Differential Non-Linearity, DNL
fC = 20 MSPS, VIN = 0.6V to 2.6V
-
±0.3
±0.5
LSB
DYNAMIC CHARACTERISTICS
Effective Number of Bits, ENOB
fIN = 1MHz
-
7.6
-
Bits
Spurious Free Dynamic Range
fIN = 1MHz
-
51
-
dB
Signal to Noise Ratio, SINAD
fC = 20MHz, fIN = 1MHz
-
46
-
dB
fC = 20MHz, fIN = 3.58MHz
-
46
-
dB
Maximum Conversion Speed, fC
VIN = 0.6V to 2.6V, fIN = 1kHz Ramp
20
35
-
MSPS
Minimum Conversion Speed
--
0.5
MSPS
Differential Gain Error, DG
NTSC 40 IRE Mod Ramp, fC = 14.3 MSPS
-
1.0
-
%
Differential Phase Error, DP
-
0.5
-
Degree
Aperture Jitter, tAJ
-30
-
ps
Sampling Delay, tDS
-4
-
ns
Data Latency, tLAT
--
2.5
Cycles
ANALOG INPUTS
Analog Input Bandwidth (-1dB), BW
-
18
-
MHz
Analog Input Capacitance, CIN
VIN = 1.5V + 0.07VRMS
-11
-
pF
RMS Signal
RMS Noise
Distortion
+
------------------------------------------------------------------
=
HI1175
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