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參數(shù)資料
| 型號(hào)： | HI1171 |
| 廠商： | Intersil Corporation |
| 英文描述： | 8-Bit, 40 MSPS, High Speed D/A Converter(8位40MHz高速D/A轉(zhuǎn)換器) |
| 中文描述： | 8位，40 MSPS的高速D / A轉(zhuǎn)換器（8位40MHz的高速的D / A轉(zhuǎn)換器） |
| 文件頁(yè)數(shù)： | 6/7頁(yè) |
| 文件大?。?/td> | 120K |
| 代理商： | HI1171 |
6
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
Detailed Description
The HI1171 is an 8-bit, current out D/A converter. The DAC
can convert at 40MHz and run on a single +5V supply. The
architecture is an encoded, switched current cell
arrangement.
Voltage Output Mode
The output current of the HI1171 can be converted into a volt-
age by connecting an external resistor to I
OUT1
. To calculate
the output resistor use the following equation:
R
OUT
= V
FS
/I
FS
,
where V
FS
can range from +0.5V to +2.0V and I
FS
can
range from 0mA to 15mA.
In setting the output current the I
REF
pin should have a resistor
connected to it that is 16 times greater than the output resistor:
R
REF
= 16 x R
OUT
As the values of both R
OUT
and R
REF
increase, power
consumption is decreased, but glitch energy and output
settling time is increased.
Clock Phase Relationship
The internal latch is closed when the clock line is high. The
latch can be cleared by the BLNK line. When BLNK is set
(HIGH) the contents of the internal data latch will be cleared.
When BLNK is low data is updated by the CLK.
Noise Reduction
To reduce power supply noise separate analog and digital
power supplies should be used with 0.1
μ
F ceramic capaci-
tors placed as close to the body of the HI1171 as possible.
The analog (AV
SS
) and digital (DV
SS
) ground returns should
be connected together back at the power supply to ensure
proper operation from power up.
17
VG
Voltage Ground, connect a 0.1
μ
F capacitor to AV
DD
.
18, 19, 22
AV
DD
Analog Supply 4.75V to 7V.
20
I
OUT1
Current Output Pin.
21
I
OUT2
Current Output pin used for a virtual ground connection. Usually connected to AV
SS
.
23, 24
DV
DD
Digital Supply 4.75V to 7V.
Pin Descriptions
(Continued)
24 PIN
SOIC
PIN
NAME
PIN DESCRIPTION
Test Circuits
FIGURE 5. MAXIMUM CONVERSION SPEED TEST CIRCUIT
OSCILLOSCOPE
8-BIT
COUNTER
WITH LATCH
CLK
40MHz
SQUARE WAVE
1
2
8
9
11
12
15
16
17
20
CLK
VB
0.1
μ
F
BLK
D7
(LSB) D0
IO
VG
V
REF
2V
I
REF
AV
DD
1k
AV
SS
3.3k
200
0.1
μ
F
HI1171
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