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參數(shù)資料
| 型號(hào)： | HI-DAC80V |
| 廠商： | Intersil Corporation |
| 英文描述： | RELAY LATCHING SPST-NO 5A 12VDC |
| 中文描述： | 12位，低成本，單片D / A轉(zhuǎn)換 |
| 文件頁(yè)數(shù)： | 4/7頁(yè) |
| 文件大?。?/td> | 68K |
| 代理商： | HI-DAC80V |
10-1037
Definitions of Specifications
Digital Inputs
The Hl-DAC80V accepts digital input codes in complementary
binary, complementary offset binary, and complementary
two’s complement binary.
Settling Time
That interval between application of a digital step input, and
final entry of the analog output within a specified window
about the settled value. Intersil Corporation usually specifies
a unipolar 10V full scale step, to be measured from 50% of
the input digital transition, and a window of
±
1
/
2
LSB about
the final value. The device output is then rated according to
the worst (longest settling) case: low to high, or high to low.
In a 12-bit system
±
1
/
2
LSB =
±
0.012% of FSR.
Slew Rate
10
15
-
V/
μ
s
INTERNAL REFERENCE
Output Voltage
6.250
+6.3
6.350
V
mA
Output Impedance
-
1.5
-
External Current
-
-
+2.5
Tempco of Drift
-
5
-
ppm/
o
C
DIGITAL INPUT
(Note 2)
Logic Levels
Logic “1”
TTL Compatible At +1
μ
A
TTL Compatible At -100
μ
A
+2
-
+5.5
V
Logic “0”
0
-
+0.8
V
POWER SUPPLY SENSITIVITY
(Notes 2, 4)
+15V Supply
-
0.001
0.002
% FSR / %V
S
% FSR / %V
S
-15V Supply
-
0.001
0.002
POWER SUPPLY CHARACTERISTICS
(Note 4)
Voltage Range
+V
S
-V
S
Current
+I
S
-I
S
NOTES:
1. Adjustable to zero using external potentiometers.
2. See Definitions.
3. FSR is “Full Scale Range: and is 20V for
±
10V range, 10V for
±
5V range, etc.
4. The HI-DAC80V/HI-DAC85V will operate with supply voltages as low as
±
11.4V. It is recommended that output voltage range -10V to
+10V not be used if the supply voltages are less than
±
12.5V.
5. With Gain and Offset errors adjusted to zero at 25
o
C.
Full Temperature
+11.4
+15
+16.5
V
Full Temperature
-11.4
-15
-16.5
V
Full Temperature, V
S
=
±
15V
Full Temperature, V
S
=
±
15V
-
+12
+15
mA
-
-15
-20
mA
Electrical Specifications
T
A
= 25
o
C, V
S
±
12V to
±
15V (Note 4), Pin 16 to Pin 24, Unless Otherwise Specified
(Continued)
PARAMETER
TEST CONDITIONS
HI-DAC80V-5, HI-DAC85V-5
UNITS
MIN
TYP
MAX
TABLE 1.
DIGITAL
INPUT
ANALOG OUTPUT
COMPLE-
MENTARY
STRAIGHT
BINARY
COMPLE-
MENTARY
OFFSET
BINARY
COMPLE-
MENTARY
TWO’S
COMPLEMENT
MSB...LSB
000...000
+ Full Scale
+ Full Scale
-LSB
100...000
Mid Scale-1 LSB
-1 LSB
+ Full Scale
111...111
Zero
- Full Scale
Zero
011...111
+
1
/
2
Full Scale
Zero
- Full Scale
Invert MSB with external inverter to obtain CTC Coding
HI-DAC80V HI-DAC85V
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