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參數(shù)資料
| 型號： | HI-8685PST-10 |
| 廠商： | HOLT INTEGRATED CIRCUITS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 384 MCELL 3 VOLT ZERO POWER ISP CPLD - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | 1 CHANNEL(S), SERIAL COMM CONTROLLER, PDSO28 |
| 封裝： | PLASTIC, SOIC-28 |
| 文件頁數(shù)： | 2/10頁 |
| 文件大?。?/td> | 239K |
| 代理商： | HI-8685PST-10 |
HI-8685, HI-8686
PIN DESCRIPTIONS
DATA RDY
OUTPUT
Receiver data ready flag. A high level indicates data is available in the receive
buffer. Flag goes low when the first 16-bit byte is read.
D0 to D15
OUTPUT
16-bit parallel data bus (tri-state)
GND
POWER
0V
INPUT
Read strobe. A low level transfers receive buffer data to the data bus
PARITY ENB
INPUT
Parity Enable - A high level activates odd parity checking which replaces the
32nd ARINC bit with an error bit. Otherwise, the 32nd ARINC bit is unchanged
ERROR
OUTPUT
Error Flag. A high level indicates a bit count error (number of ARINC bits was
less than or greater than 32) and/or a parity error if parity detection was enabled
(PARITY ENB high)
RINA/RINA-10
INPUT
Positive direct ARINC serial data input
RINB/RINB-10
INPUT
Negative direct ARINC serial data input (both RINB and RINB-10 on HI-8686)
INPUT
Internal logic states are initialized with a low level
TESTA
INPUT
Used in conjunction with the TESTB input to bypass the built-in analog line
receiver circuitry
TESTB
INPUT
U
receiver circuitry
GAPCLK
INPUT
Gap Clock. Determines the minimum time required between ARINC words for
detection. The minimum word gap time is between 16 and 17 clock cycles of
this signal.
Vcc
POWER
+5V ±10% supply
SIGNAL
FUNCTION
DESCRIPTION
READ
RESET
(both RINA and RINA-10 on HI-8686)
sed in conjunction with the TESTA input to bypass the built-in analog line
FUNCTIONAL DESCRIPTION
TheHI-8685 and HI-8686are serialto16-bitparallelconvert-
ers. Theincomingdatastreamisseriallyshiftedintoaninput
register,checkedforerrors,andthentransferredinparallelto
a32-bitreceive buffer. Thereceivedatacanbeaccessedus-
ing two 16-bit parallel read operations while the next serial
datasteamisbeingreceived.
TheblockdiagramforboththeHI-8685andHI-8685-10prod-
ucts is found in Figure 1. Both have built-in receivers elimi-
nating the need for additional external ARINC level detection
circuitry. Theonlydifferencebetweenthetwoproductsisthe
amount of internal resistance in series with each ARINC in-
put.
Typically35K
RINB ARINC 429 inputs. They connect to level translators
whoseresistancetoGNDistypically10K
resistors are in series with both the RINA and
Afterleveltrans-
RECEIVERINPUTS
HI-8685ARINCINPUTS(RINA&RINB)
.
lation, the buffered inputs drive a differential amplifier. The
differentialsignaliscomparedtolevelsderivedfromadivider
betweenVCCandGND. Thenominalsettingscorrespondto
aOne/Zeroamplitudeof6.0VandaNullamplitudeof3.3V. A
valid ARINC One/Zero input sets a latch and a Null input re-
setsthelatch.
Sinceanyaddedexternalseriesresistancewillaffectthevolt-
age translation, the HI-8685-10 product has only 25K
the 35K
series resistance required for proper ARINC 429
level detection. The remaining 10K
the user for incorporation in external circuitry such as for
lightningprotection.
of
required is available to
TheHI-8686hasbothsetsofARINCinputs,RINA/RINA-10
andRINB/RINB-10availabletotheuser.
HI-8685-10ARINCINPUTS(RINA-10&RINB-10)
HI-8686ARINCINPUTS
HOLT INTEGRATED CIRCUITS
2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HI-8686 | ARINC INTERFACE DEVICE ARINC 429& 561 SERIAL DATA TO 16-BIT PARALLEL DATA |
| HI-8686PQI | 384 MCELL 3 VOLT ZERO POWER ISP CPLD - NOT RECOMMENDED for NEW DESIGN |
| HI-8686PQT | ARINC INTERFACE DEVICE ARINC 429& 561 SERIAL DATA TO 16-BIT PARALLEL DATA |
| HI-8783PDT | ARINC INTERFACE DEVICE 8-BIT PARALLEL DATA CONVERTED 429&561 SERIAL DATA OUT |
| HI-8783 | 384 MCELL 3 VOLT ZERO POWER ISP CPLD - NOT RECOMMENDED for NEW DESIGN |
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