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參數(shù)資料
| 型號： | HI-8685PJT-10 |
| 廠商： | HOLT INTEGRATED CIRCUITS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | ARINC INTERFACE DEVICE ARINC 429& 561 SERIAL DATA TO 16-BIT PARALLEL DATA |
| 中文描述： | 1 CHANNEL(S), SERIAL COMM CONTROLLER, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 239K |
| 代理商： | HI-8685PJT-10 |
HI-8685, HI-8686
PROTOCOLDETECTION
The ARINC clock and One/Zero data that are derived from
the
outputsof the built-in line receiver isillustrated in
Figure 3. The resulting steam of digitaldata is shifted into a
32-bitinputregister.
The ARINC clock and One/Zero data can also be created
from the TESTA and TESTB inputs as shown in Figure 4.
When either test input is high, the built-in analog line driver
isdisabled.
digital
For ARINC 561 operation, the TESTA and TESTB digitalin-
putdatastreamsmustbederivedfromtheARINC561data,
clockandsyncwithexternallogic.
GAPDETECTION
The end of a data word is detected by an internal counter
that times out when a data One or Zero is not received for a
period equal to 16 cycles of the GAPCLK signal. The gap
detection time may vary between 16 and 17 cycles of the
GAPCLK signal since the incoming data and GAPCLK are
not usually synchronous inputs. The required frequency of
GAPCLK is a function of the mininum gap time specified for
the type of ARINC data being received. Table 1 indicates
typical frequencies that may be used for the various data
ratesnormallyencountered.
BIT
COUNT
PARITY
DETECT
GAP
DETECT
32-BIT
SHIFT
REG.
32-BIT
RECEIVE
BUFFER
32-BIT
TO
16-BIT
MUX
ERROR
DETECT
CLOCK
&
DATA
DETECT
PARITY
ENB
RINB
TESTA
TESTB
GAPCLK
RESET
BYTE
COUNT
READ
DATA RDY
ERROR
32
16
32
Figure 1. Block Diagram
ESD
PROTECTION
&
LINE
RECEIVER
DATABUS
TYPE
BIT PERIOD
( s)
MINIMUM GAP
( s)
GAP CLOCK
MHz
GAP DETECTION
TIME ( s)
429
10
45
0.75
1.0
1.5
21.3 - 22.7
16 - 17
10.7 - 11.3
429
69 - 133
310 - 599
0.1
160 - 170
575
69 - 133
310 - 599
0.1
160 - 170
561
69 - 133
103 - 200
0.2
80 - 85
Table 1 - Typical Gap Detection Times
FUNCTIONAL DESCRIPTION (cont.)
RXA
RXB
10K
BIT 32
BIT 32
RINA
10K
D0 - D15
25K
25K
RINB-10
RINA-10
DATA
CLK
HOLT INTEGRATED CIRCUITS
3
相關(guān)PDF資料 |
PDF描述 |
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| HI-8685 | 384 MCELL 3 VOLT ZERO POWER ISP CPLD - NOT RECOMMENDED for NEW DESIGN |
| HI-8685PJT | ARINC INTERFACE DEVICE ARINC 429& 561 SERIAL DATA TO 16-BIT PARALLEL DATA |
| HI-8685PSI | ARINC INTERFACE DEVICE ARINC 429& 561 SERIAL DATA TO 16-BIT PARALLEL DATA |
| HI-8685PSI-10 | 384 MCELL 3 VOLT ZERO POWER ISP CPLD - NOT RECOMMENDED for NEW DESIGN |
| HI-8685PST | ARINC INTERFACE DEVICE ARINC 429& 561 SERIAL DATA TO 16-BIT PARALLEL DATA |
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