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參數(shù)資料
| 型號： | HI-8685PJI-10 |
| 廠商： | HOLT INTEGRATED CIRCUITS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | ARINC INTERFACE DEVICE ARINC 429& 561 SERIAL DATA TO 16-BIT PARALLEL DATA |
| 中文描述： | 1 CHANNEL(S), SERIAL COMM CONTROLLER, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 4/10頁 |
| 文件大小： | 239K |
| 代理商： | HI-8685PJI-10 |
HI-8685, HI-8686
Onceawordgapisdetected,thedatawordintheinputreg-
isteristransferred to the receive buffer and checked for er-
rors.
When parity detection is enabled (PARITY ENB high), the
received word is checked for odd parity. If there is a parity
error,the32ndbitofthereceiveddatawordissethigh.
If parity checking is disabled (PARITY ENB low) the 32nd
bitofthedatawordisalwaysthe32ndARINCbitreceived.
The ERROR flag output is set high upon receipt of a word
gap and the number of bits received since the previous
word gap is less than or greater than 32. The ERROR flag
is reset low when the next valid ARINC word is written into
thereceivebufferorwhen
RESET
ispulsedlow.
Whenthedata word istransferredto thereceive buffer, the
DATA RDY pingoeshigh. The data wordcan thenbe read
in two 16-bit bytes by pulsing the
cated in Figure 5. The first read cycle resets DATA RDY
low and increments an internal counter to the second
16-bit byte.
The relationship between each bit of an
ARINC word received and each bit of the two 16-bit data
busbytesisspecifiedinFigure2.
input low as indi-
When a new ARINC word is received it always overwrites
the receive buffer. If the first byte of the previous word has
not been read, then previous data is lost and the receive
buffer will contain the new ARINC word. However, if the
DATA RDY pin goes high between the reading of the first
and second bytes, the first byte is no longer valid because
the corresponding second byte has been overwritten by
thenewARINCword. Also,thenextreadwillbe ofthefirst
byteofthenewARINCwordsincetheinternalbytecounter
is always reset to the first byte when new data is trans-
ferredtothereceivebuffer.
ERRORCHECKING
READINGRECEIVEBUFFER
READ
FUNCTIONAL DESCRIPTION (cont.)
TRUTH TABLE 1.
RINA(-10)
RINB(-10)
TESTA
TESTB
RXA
RXB
-1.50Vto+1.50V
-1.50Vto+1.50V
0
0
0
0
-3.25Vto-6.50V
+3.25Vto+6.50V
0
0
0
1
+3.25Vto+6.50V
-3.25Vto-6.50V
0
0
1
0
X
X
0
1
0
1
X
X
1
0
1
0
X
X
1
1
0
0
X=don'tcare
Read
Byte
Data Bus Bits
ARINC Bits
1st
2nd
Byte 1
Byte 2
D0 - D15
D0 - D15
ARINC 1 - ARINC 16
ARINC 17 - ARINC 32
FIGURE 2. ORDER OF RECEIVED DATA
RESET
TEST MODE
A lowonthe
internallogic. When
mains in the initialized state until the first word gap is de-
tectedpreventing receptionofapartialword.
inputsetsaflip-flopwhichinitializesthe
goeshigh,theinternallogicre-
RESET
Thebuilt-indifferentiallinereceivercanbedisabledallowing
the data and clock detection circuitry to be driven directly
with digital signals. The logical OR function of the TESTA
and TESTB is defined in Truth Table 1. The two inputs can
beusedfortestingthereceiverlogicandforinputtingARINC
429 type data derived from another source/ protocol. See
Figure4fortypicaltestinputtiming.
The device should always be initialized with
diately after entering the test mode to clear a partial word
that may have been received since the last word gap. Oth-
erwise, an ERROR condition may occur and the first 32 bits
of data on the test inputs may not be properly received.
imme-
Also, when entering the test mode, both TESTA and TESTB
should be set high and held in that state for at least one
word gapperiod (17 gap clocks)after
goeshigh.
When exiting the test mode, both test inputs should be held
lowandthedeviceinitializedwith
RESET
RESET
RESET
RESET.
HOLT INTEGRATED CIRCUITS
4
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