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參數(shù)資料
| 型號： | HI-8684PST-10 |
| 廠商： | HOLT INTEGRATED CIRCUITS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 384 MCELL 3 VOLT ZERO POWER ISP CPLD - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | 1 CHANNEL(S), SERIAL COMM CONTROLLER, PDSO20 |
| 封裝： | PLASTIC, SOIC-20 |
| 文件頁數(shù)： | 2/10頁 |
| 文件大?。?/td> | 172K |
| 代理商： | HI-8684PST-10 |
HI-8683, HI-8684
PIN DESCRIPTIONS
DATA RDY
OUTPUT
Receiver data ready flag. A high level indicates data is available in the receive
buffer. Flag goes low when the first 8-bit byte is read.
D1 to D7
OUTPUT
8-bit parallel data bus (tri-state)
GND
POWER
0V
INPUT
Read strobe. A low level transfers receive buffer data to the data bus
PARITY ENB
INPUT
Parity Enable - A high level activates odd parity checking which replaces the
32nd ARINC bit with an error bit. Otherwise, the 32nd ARINC bit is unchanged
ERROR
OUTPUT
Error Flag. A high level indicates a bit count error (number of ARINC bits was
less than or greater than 32) and/or a parity error if parity detection was enabled
(PARITY ENB high)
INA
INPUT
Positive digital serial data input (HI-8683 only)
INB
INPUT
Negative digital serial data input (HI-8683 only)
RINA/RINA-10
INPUT
Positive direct ARINC serial data input
RINB/RINB-10
INPUT
Negative direct ARINC serial data input (HI-8684 & HI-8684-10 only)
INPUT
Internal logic states are initialized with a low level
TESTA
INPUT
Used in conjunction with the TESTB input to bypass the built-in analog line
receiver circuitry
(HI-8684 & HI-8684-10 only)
TESTB
INPUT
U
receiver circuitry (HI-8684 & HI-8684-10 only)
GAPCLK
INPUT
Gap Clock. Determines the minimum time required between ARINC words for
detection. The minimum word gap time is between 16 and 17 clock cycles of
this signal.
Vcc
POWER
+5V ±10% supply
SIGNAL
FUNCTION
DESCRIPTION
READ
RESET
(HI-8684 & HI-8684-10 only)
sed in conjunction with the TESTA input to bypass the built-in analog line
HOLT INTEGRATED CIRCUITS
2
FUNCTIONAL DESCRIPTION
The HI-8683 and HI-8684 are serial to 8-bit parallel convert-
ers. Theincomingdatastreamisseriallyshiftedintoaninput
register,checkedforerrors,andthentransferredinparallelto
a32-bitreceive buffer. Thereceivedatacanbeaccessedus-
ing four 8-bit parallel read operations while the next serial
datasteamisbeingreceived.
Figure 1 is a block diagram of both the HI-8683 and HI-8684.
The difference between the two products is the HI-8684 has
abuilt-inlinereceiverwhereastheHI-8683is strictlyadigital
device and requires an external ARINC line receiver such as
the Holt HI-8482, HI-8588 or HI-8590 to interface to the
ARINC429bus.
RECEIVERINPUTS
HI-8684LineReceiver
Typically35K
RINB ARINC 429 inputs. They connect to level translators
whoseresistancetoGNDistypically10K
lation, the buffered inputs drive a differential amplifier. The
differentialsignaliscomparedtolevelsderivedfromadivider
betweenVCCandGND. Thenominalsettingscorrespondto
aOne/Zeroamplitudeof6.0VandaNullamplitudeof3.3V. A
valid ARINC One/Zero input sets a latch and a Null input re-
setsthelatch.
resistorsare inserieswith both the RINA and
Afterleveltrans-
Sinceanyaddedexternalseriesresistancewillaffectthevolt-
agetranslation,the HI-8684-10isavailablewith 25K
35K
series resistance required for proper ARINC 429 level
detection. Theremaining10K
can be incorporated in other external circuitry such as light-
ning protection. Except for the different input series resis-
tance,the HI-8684andHI-8684-10areidentical.
ofthe
requiredthatmustbeadded
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HI-8683PDI | ARINC INTERFACE DEVICE ARINC 429& 561 SERIAL DATA TO 8-BIT PARALLEL DATA |
| HI-8684PJI | ARINC INTERFACE DEVICE ARINC 429& 561 SERIAL DATA TO 8-BIT PARALLEL DATA |
| HI-8684PJI-10 | ARINC INTERFACE DEVICE ARINC 429& 561 SERIAL DATA TO 8-BIT PARALLEL DATA |
| HI-8684PJT | ARINC INTERFACE DEVICE ARINC 429& 561 SERIAL DATA TO 8-BIT PARALLEL DATA |
| HI-8684PJT-10 | ARINC INTERFACE DEVICE ARINC 429& 561 SERIAL DATA TO 8-BIT PARALLEL DATA |
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