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參數(shù)資料
| 型號： | HI-8683 |
| 廠商： | Holt Integrated Circuits |
| 英文描述： | 384 MCELL 3 VOLT ZERO POWER ISP CPLD - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | ARINC公司接口設(shè)備的ARINC 429 |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 172K |
| 代理商： | HI-8683 |
HI-8683, HI-8684
HOLT INTEGRATED CIRCUITS
4
ERRORCHECKING
READINGRECEIVEBUFFER
Onceawordgapisdetected,thedatawordintheinputreg-
isteristransferred to the receive buffer and checked for er-
rors.
When parity detection is enabled (PARITY ENB high), the
received word is checked for odd parity. If there is a parity
error,the32ndbitofthereceiveddatawordissethigh.
If parity checking is disabled (PARITY ENB low) the 32nd
bitofthedatawordisalwaysthe32ndARINCbitreceived.
The ERROR flag output is set high upon receipt of a word
gap and the number of bits received since the previous
word gap is less than or greater than 32. The ERROR flag
is reset low when the next valid ARINC word is written into
thereceivebufferorwhen
RESET
ispulsedlow.
Whenthedata word istransferredto thereceive buffer, the
DATA RDY pingoeshigh. The data wordcan thenbe read
in four 8-bit bytes by pulsing the
cated in Figure 5. The first read cycle resets DATA RDY
low and increments an internal counter to the next 8-bit
byte. Thecountercontinuestoincrementoneachreadcy-
cle until all four bytes are read. The relationship between
eachbitofanARINCwordreceivedandeachbitofthefour
8-bitdatabusbytesisspecifiedinFigure2.
input low as indi-
When a new ARINC word is received it always overwrites
the receive buffer. If the first byte of the previous word has
not been read, then previous data is lost and the receive
buffer will contain the new ARINC word. However, if the
DATA RDY pin goes high between the reading of the first
and fourth bytes, the previous read bytes are no longer
valid because the unread bytes have been overwritten by
thenewARINCword. Also,thenextreadwillbe ofthefirst
byteofthenewARINCwordsincetheinternalbytecounter
is always reset to the first byte when new data is trans-
ferredtothereceivebuffer.
READ
FUNCTIONAL DESCRIPTION (cont.)
TRUTH TABLE 1.
RINA
RINB
TESTA
TESTB
RXA
RXB
-1.50to+1.50V
-1.50Vto+1.50V
0
0
0
0
-3.25Vto-6.50V
+3.25Vto+6.50V
0
0
0
1
+3.25Vto+6.50V
-3.25Vto-6.50V
0
0
1
0
X
X
0
1
0
1
X
X
1
0
1
0
X
X
1
1
0
0
X=don'tcare
Read
Byte
Data Bus Bits
ARINC Bits
1st
2nd
3rd
4th
Byte 1
Byte 2
Byte 3
Byte 4
D0 - D7
D0 - D7
D0 - D7
D0 - D7
ARINC 1 - ARINC 8
ARINC 9 - ARINC 16
ARINC 17 - ARINC 24
ARINC 25 - ARINC 32
FIGURE 2. ORDER OF RECEIVED DATA
RESET
TEST MODE(HI-8684only)
A low on the
the internal logic. When
logicremainsintheinitializedstateuntilthefirstwordgapis
detectedpreventing receptionofapartialword.
input sets a flip-flop which initializes
goes high, the internal
RESET
The built-in differential line receiver on the HI-8684 can be
disabled allowing the data and clock detection circuitry to
be driven directly with digital signals. The logical OR func-
tion of the TESTA and TESTB is defined in Truth Table 1.
Thetwoinputscanbeusedfortestingthereceiverlogicand
for inputting ARINC 429 type data derived from another
source/protocol. SeeFigure4fortypicaltestinputtiming.
The device should always be initialized with
diately after entering the test mode to clear a partial word
that may have been received since the last word gap. Oth-
erwise, an ERROR condition may occur and the first 32
bits of data on the test inputs may not be properly re-
ceived.
imme-
Also, when entering the test mode, both TESTA and
TESTB should be set high and held in that state for at
least one word gap period (17 gap clocks) after
goes high.
Whenexitingthetestmode,bothtestinputsshouldbeheld
lowandthedeviceinitializedwith
RESET
RESET
RESET
RESET.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HI-8683PSI | ARINC INTERFACE DEVICE ARINC 429& 561 SERIAL DATA TO 8-BIT PARALLEL DATA |
| HI-8683PST | ARINC INTERFACE DEVICE ARINC 429& 561 SERIAL DATA TO 8-BIT PARALLEL DATA |
| HI-8684PSI | 384 MCELL 3 VOLT ZERO POWER ISP CPLD - NOT RECOMMENDED for NEW DESIGN |
| HI-8684PSI-10 | ARINC INTERFACE DEVICE ARINC 429& 561 SERIAL DATA TO 8-BIT PARALLEL DATA |
| HI-8684PST | ARINC INTERFACE DEVICE ARINC 429& 561 SERIAL DATA TO 8-BIT PARALLEL DATA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HI-8683PST | 制造商:Holt Integrated Circuits 功能描述:ARINC Interface Device 20-Pin SOIC W |
| HI-8733 | 制造商:HANNA INSTRUMENTS 功能描述:CONDUCTIVITY METER |
| HI-8733N | 制造商:HANNA INSTRUMENTS 功能描述:CONDUCTIVITY METER 制造商:HANNA INSTRUMENTS 功能描述:CONDUCTIVITY METER; Conductivity Range:0S/cm to 1999S/cm; Accuracy %:1%; Calibration Type:Temperature; External Height:185mm; External Width:82mm; External Depth:45mm; Weight:355g; Accuracy: 1% full scale; Battery Lifetime:100h; |
| HI8783PSI | 制造商:Holt Integrated Circuits 功能描述:ARINC Interface Device 20-Pin SOIC W |
| HI-8783PSIF | 制造商:Holt Integrated Circuits 功能描述: |
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