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參數資料
| 型號： | HI-8588PSI |
| 廠商： | HOLT INTEGRATED CIRCUITS INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | ARINC 429 LINE RECEIVER |
| 中文描述： | LINE RECEIVER, PDSO8 |
| 封裝： | PLASTIC, SOIC-8 |
| 文件頁數： | 2/6頁 |
| 文件大?。?/td> | 125K |
| 代理商： | HI-8588PSI |
TEST
HI-8588-10
FUNCTIONAL DESCRIPTION
TXBOUT
TXAOUT
TX1IN
TX0IN
ARINC
Channel
RINB
RINA
TESTA
TESTB
HI-8588-10
{
HARDWIRE
OR
DRIVE FROM LOGIC
ROUTB
ROUTA
VCC
V-
-15V
GND
4
TXD0
TXD1
RXD0
RXD1
HI-6010
8 BIT BUS
ARINC
Channel
1
2
8
6
7
4
3
5
6
7
2
3
FIGURE 2 - APPLICATION DIAGRAM
APPLICATION INFORMATION
15V
V+
8
5
HI-8586
SLP1.5
1
RECEIVER
Figure 1 shows the general architecture of the ARINC 429
receiver. The receiver operates off the VCC supply only.
The inputs RINA and RINB each require 35K
tance of which 25K
is internal to the chip. The series re-
sistanceisconnectedtoleveltranslatorswhoseresistance
to Ground is typically 10K . In order for the voltage trans-
lationnottobeadverselyaffected,anexternal10K
resister must be added to each ARINC input.
HI-8588-10 device is typically chosen for applications
where external series resistors are required in its lightning
protectioncircuitry.
of resis-
series
The
After level translation, the inputs are buffered and become
inputstoadifferentialamplifier. Theamplitudeofthediffer-
ential signal is compared to levels derived from a divider
Figure 2 shows a possible application of the
HI-8588interfacinganARINCreceivechannel
to the HI-6010 which in turn interfaces to an
8-bitbus.
RINA
RINB
NULL
ZERO
NULL
ONE
TESTA
ROUTB
ROUTA
FIGURE 1 - RECEIVER BLOCK DIAGRAM
S
LATCH
Q
R
LATCH
ESD
PROTECTION
AND
TRANSLATION
10K
10K
between VCC and Ground. The nominal settings corre-
spond to a One/Zero amplitude of6.0V and a Null ampli-
tudeof3.3V.
ThestatusoftheARINCreceiverinputislatched. ANull
input resets the latches and a One or Zero input sets the
latches.
The logic at the output is controlled by the test signal
which is generated by the logical OR of the TestA and
TestB pins. Unlike the HI-8588, if TestA and TestB are
bothOne,theHI-8588-10outputsarepulledlow instead
of being tri-stated. This allows the digital outputs of a
transmitter to be connected to the test inputs through
controllogicforself-testpurposes.
GND
S
Q
TESTB
R
TESTA
TESTB
TEST
HOLT INTEGRATED CIRCUITS
2
相關PDF資料 |
PDF描述 |
|---|---|
| HI-8588PSI-10 | ARINC 429 LINE RECEIVER |
| HI-8588PST | ARINC 429 LINE RECEIVER |
| HI-8588PST-10 | ARINC 429 LINE RECEIVER |
| HI-8588 | 384 MCELL 3 VOLT ZERO POWER ISP CPLD - NOT RECOMMENDED for NEW DESIGN |
| HI-8588CRM-10 | ARINC 429 LINE RECEIVER |
相關代理商/技術參數 |
參數描述 |
|---|---|
| HI-8588PSI-10 | 制造商:Holt Integrated Circuits 功能描述:ARINC 429 Line Receiver 8-Pin SOIC N |
| HI-8588PSIF | 制造商:Holt Integrated Circuits 功能描述:ARINC 429 Line Receiver 8-Pin SOIC N |
| HI-8588PSIF-10 | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:ARINC 429 LINE RECEIVER |
| HI-8588PSM | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:ARINC 429 LINE RECEIVER |
| HI-8588PSM-10 | 制造商:Holt Integrated Circuits 功能描述:ARINC 429 Line Receiver 8-Pin SOIC N |
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