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參數(shù)資料
| 型號： | HI-8582CJI-10 |
| 廠商： | HOLT INTEGRATED CIRCUITS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | ARINC 429 SYSTEM ON A CHIP |
| 中文描述： | 1 CHANNEL(S), 125K bps, SERIAL COMM CONTROLLER, CQCC52 |
| 封裝： | CERQUAD-52 |
| 文件頁數(shù)： | 13/15頁 |
| 文件大?。?/td> | 419K |
| 代理商： | HI-8582CJI-10 |
VDD = 5V, V+=10V, V-=-10V, GND = 0V, TA = Oper. Temp. Range and fclk=1MHz 0.1% with 60/40 duty cycle
LIMITS
PARAMETER
SYMBOL
UNITS
MIN
TYP
MAX
CONTROL WORD TIMING
RECEIVER FIFO AND LABEL READ TIMING
TRANSMITTER FIFO AND LABEL WRITE TIMING
TRANSMISSION TIMING
LINE DRIVER OUTPUT TIMING
Pulse Width -
t
t
t
50
50
0
ns
ns
ns
Setup - DATA BUS Valid to
Hold -
CWSTR
HIGH
HIGH to DATA BUS Hi-Z
Delay - Start ARINC 32nd Bit to
LOW: High Speed
Low Speed
t
t
16
128
μs
μs
Delay -
Delay -
LOW to
LOW to
L0W
HIGH
t
t
0
ns
ns
250
350
Setup - SEL to
Hold - SEL to
L0W
HIGH
t
t
0
0
ns
ns
Delay -
Delay -
L0W to DATA BUS Valid
HIGH to DATA BUS Hi-Z
t
t
60
50
100
80
ns
ns
Pulse Width -
L0W (Same ARINC Word)
LOW (Next ARINC Word)
EN
or
t
60
60
200
ns
ns
ns
Spacing -
Spacing -
HIGH to next
HIGH to next
EN
t
t
Pulse Width -
or
t
50
ns
Setup - DATA BUS Valid to
Hold -
HIGH to DATA BUS Hi-Z
PL
HIGH
t
t
50
0
ns
ns
Spacing -
or
t
LABEL
85
200
ns
ns
Spacing between Label Write pulses
t
Delay -
HIGH to TX/R LOW
t
300
ns
Spacing -
HIGH to ENTX HIGH
t
0
μs
Delay - 32nd ARINC Bit to TX/R HIGH
t
50
ns
Spacing - TX/R HIGH to ENTX L0W
t
0
ns
Line driver transition differential times:
(High Speed, control register CR13 = Logic 0)
high to low
low to high
t
t
1.0
1.0
1.5
1.5
2.0
2.0
CWSTR
CWSTR
D/R
D/R
EN
EN
D/R
EN
EN
EN
EN
EN1
EN2
EN
EN
PL1
PL2
PL
PL1
PL2
PL2
PL2
CWSTR
CWSET
CWHLD
D/R
D/R
D/REN
END/R
SELEN
ENSEL
ENDATA
DATAEN
EN
ENEN
READEN
PL
DWSET
DWHLD
PL12
TX/R
PL2EN
DTX/R
ENTX/R
fx
rx
Delay - ENTX HIGH to TXAOUT or TXBOUT: High Speed
Delay - ENTX HIGH to TXAOUT or TXBOUT: Low Speed
t
t
25
200
ENDAT
ENDAT
μs
μs
μs
μs
HI-8582, HI-8583
REPEATER OPERATION TIMING
Hold -
HIGH to
HIGH
tPLEN
0
ns
Delay - TX/R LOW to ENTX HIGH
tTX/REN
0
ns
Master Reset Pulse Width
tMR
50
ns
ARINC Data Rate and Bit Timing
± 1%
PL
EN
Delay -
LOW to
LOW
tENPL
0
ns
EN
PL
HOLT INTEGRATED CIRCUITS
13
相關PDF資料 |
PDF描述 |
|---|---|
| HI-8582CJI | ARINC 429 SYSTEM ON A CHIP |
| HI-8582CJT | ARINC 429 SYSTEM ON A CHIP |
| HI-8582CJT-10 | ARINC 429 SYSTEM ON A CHIP |
| HI-8582 | 384 MCELL 3 VOLT ZERO POWER ISP CPLD - NOT RECOMMENDED for NEW DESIGN |
| HI-8582PQI | 384 MCELL 3 VOLT ZERO POWER ISP CPLD - NOT RECOMMENDED for NEW DESIGN |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HI-8582CJIF | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:ARINC 429 System on a Chip |
| HI-8582CJIF-10 | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:ARINC 429 System on a Chip |
| HI-8582CJT | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:ARINC 429 SYSTEM ON A CHIP |
| HI-8582CJT-10 | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:ARINC 429 SYSTEM ON A CHIP |
| HI-8582CJTF | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:ARINC 429 System on a Chip |
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