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參數(shù)資料
| 型號： | HI-8282S |
| 廠商： | HOLT INTEGRATED CIRCUITS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 256 MACROCELL 3.3 VOLT ISP CPLD - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | 1 CHANNEL(S), 125K bps, SERIAL COMM CONTROLLER, CQCC44 |
| 封裝： | ROHS COMPLIANT, CERAMIC, LCC-44 |
| 文件頁數(shù)： | 5/14頁 |
| 文件大?。?/td> | 448K |
| 代理商： | HI-8282S |
TRANSMITTER
AblockdiagramofthetransmittersectionisshowninFigure3.
TheFIFOisloadedsequentiallybyfirstpulsing
andthen
toloadbyte2. Thecontrollogicautomaticallyloads
the 31 bit word in the next available position of the FIFO. If TX/R,
the transmitter ready flag is high (FIFO empty), then 8 words,
each 31 bits long, may be loaded. If TX/R is low, then only the
available positions may be loaded. If all 8 positions are full, the
FIFOignoresfurtherattemptstoloaddata.
toloadbyte1
When ENTX goes high, enabling transmission, the FIFO
positions are incremented with the top register loading into the
data transmission shift register. Within 2.5 data clocks the first
data bit appears at either 429DO or
data transmission shift register are presented sequentially to the
outputsintheARINC429formatwiththefollowingtiming:
. The 31 bits in the
429DO
ARINCDATABITTIME
DATABITTIME
NULLBITTIME
WORDGAPTIME
10Clocks
5Clocks
5Clocks
40Clocks
80Clocks
40Clocks
40Clocks
320Clocks
The word counter detects when all loaded positions are
transmittedandsetsthetransmitterreadyflag,TX/R,high.
FIFOOPERATION
DATATRANSMISSION
PL1
PL2
HIGHSPEED
LOWSPEED
TRANSMITTERPARITY
The parity generator counts the ONES in the 31-bit word. If the
BD12 control word bit is set low, the 32nd bit transmitted will make
parityodd. Ifthecontrolbitishightheparityiseven.
If the BD05 control word bit is set low, 429DO or
inputstothereceiverbypassingtheinterfacecircuitry.
become
The two receivers are independent of the transmitter. Therefore,
controlofdataexchangesarestrictlyattheoptionoftheuser. The
onlyrestrictionsare:
1. The received data may be overwritten if not retrieved
withinoneARINCwordcycle.
2. The FIFO can store 8 words maximum and ignores
attemptstoloadadditiondataiffull.
3. Byte1ofthetransmitterdatamustbeloadedfirst.
4. Either byte of the received data may be retrieved first.
Bothbytesmustberetrievedtoclearthedatareadyflag.
5. After ENTX, transmission enable, goes high it cannot go
low until TX/R, transmitter readyflag, goes high. Otherwise,
oneARINCwordislostduringtransmission.
SELFTEST
SYSTEMOPERATION
429DO
HOLT INTEGRATED CIRCUITS
4-33
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HI-8282ST | ARINC 429 SERIAL TRANSMITTER AND DUAL RECEIVER |
| HI-8282U | ARINC 429 SERIAL TRANSMITTER AND DUAL RECEIVER |
| HI-8282 | 256 MACROCELL 3.3 VOLT ISP CPLD - NOT RECOMMENDED for NEW DESIGN |
| HI-8282SM-01 | ARINC 429 SERIAL TRANSMITTER AND DUAL RECEIVER |
| HI-8282J-44 | ARINC 429 SERIAL TRANSMITTER AND DUAL RECEIVER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HI-8282SM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Transceiver |
| HI-8282SM-01 | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:ARINC 429 SERIAL TRANSMITTER AND DUAL RECEIVER |
| HI-8282SM-03 | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:ARINC 429 SERIAL TRANSMITTER AND DUAL RECEIVER |
| HI-8282ST | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:ARINC 429 SERIAL TRANSMITTER AND DUAL RECEIVER |
| HI8282U | 制造商:Intersil Corporation 功能描述: |
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