參數(shù)資料
型號(hào): HI-8282ACLT
廠商: HOLT INTEGRATED CIRCUITS INC
元件分類(lèi): 微控制器/微處理器
英文描述: XCR3256XL-12FTG256C - NEW PRODUCT
中文描述: 1 CHANNEL(S), 125K bps, SERIAL COMM CONTROLLER, CQCC44
封裝: CERAMIC, LCC-44
文件頁(yè)數(shù): 6/14頁(yè)
文件大小: 688K
代理商: HI-8282ACLT
REPEATEROPERATION
The repeater mode of operation allows a data word that has been
received by the HI-8282A to be placed directly into its FIFO for
transmission. After a 32-bit word has been shifted into the receiver
shiftregister,the
flagwillgolow. Alogic"0"isplacedontheSEL
line and
is strobed. This is the same procedure as for normal
receiver operation and it places the lower byte (16) of the data word
on the data bus. By strobing
PL1
at the same
D/R
EN
time as
, the byte
EN
HI-8282A
willalsobeplacedintothetransmitterFIFO. SEListhentakenhigh
and
is strobed again to place the upper byte of the data word on
the data bus. By strobing
at the same time as
bytewillalsobeplacedintotheFIFO. Thedatawordisnowreadyto
be transmitted according to the parity programmed into the control
wordregister.
, the second
EN
Innormaloperation,eitherbyteofareceiveddatawordmayberead
from the receiver latches first by use of SEL input. During repeater
operation however, the lower byte of the data word must be read
first. This is necessary because, as the data is being read, it is also
being loaded into the FIFO and the transmitter FIFO is always
loadedwiththelowerbyteofthedatawordfirst.
EN
PL2
429DO
429DO
ARINC BIT
NULL
DATA
DATA
DATA
NULL
NULL
WORD GAP
BIT 1
NEXT WORD
BIT 32
BIT 31
BIT 30
CWHLD
t
CWSET
t
CWSTR
t
DATA BUS
CWSTR
VALID
DATA BUS
SELEN
t
D/R
t
ENSEL
t
DATAEN
t
D/REN
t
END/R
t
EN
t
ENSEL
t
SELEN
t
DATAEN
t
ENDATA
t
ENDATA
t
ENEN
t
BYTE 1 VALID
BYTE 2 VALID
HOLT INTEGRATED CIRCUITS
6
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