參數(shù)資料
型號: HI-8282A
廠商: Holt Integrated Circuits
英文描述: ARINC 429 SERIAL TRANSMITTER AND DUAL RECEIVER
中文描述: ARINC公司429串行發(fā)送器和雙接收機
文件頁數(shù): 4/14頁
文件大小: 688K
代理商: HI-8282A
HI-8282A
RECEIVER LOGICOPERATION
BITTIMING
BITRATE
PULSERISETIME
PULSEFALLTIME
PULSEWIDTH
Figure2showsablockdiagramofthelogicsectionofeach receiver.
The ARINC 429 specification contains the following timing
specificationforthereceiveddata:
100KBPS±1%
1.5±0.5μsec
1.5±0.5μsec
5μsec±5%
12K-14.5KBPS
10±5μsec
10±5μsec
34.5to41.7μsec
Again the HI-8282A accepts signals that meet these specifications
and rejects outside the tolerances.
achievesthisisdescribedbelow:
The way the logic operation
1. Keytothe performanceof thetimingchecking logic isanac-
curate 1MHz clock source.
recommmended.
Less than 0.1% error is
2. The sampling shift registers are 10 bits long and must show
three consecutive Ones, Zeros or Nulls to be considered valid
data. Additionally,fordatabits,theOne orZerointheupperbits
of the sampling shift registers must be followed by a Null in the
lowerbitswithinthedatabittime.
three consecutive Nulls must be found in both the upper and
lowerbitsofthesamplingshift register. In this manner the mini-
mumpulsewidthisguaranteed.
For a Null in the word gap,
HIGHSPEED
LOWSPEED
FUNCTIONAL DESCRIPTION (con't)
3. Each data bit must follow its predecessor by not less than
8 samples and no more than 12 samples. In this manner the
bit rate is checked. With exactly 1MHz input clock frequency,
theacceptabledatabitratesareasfollows:
83KBPS
125KBPS
10.4KBPS
15.6KBPS
4. The Word Gap timer samples the Null shift register every
10 input clocks (80 for low speed) after the last data bit of a
validreception. IftheNullispresent,theWordGapcounter is
incremented. Acountof3willenablethenextreception.
The receiver parity circuit counts Ones received, including the
parity bit, ARINC bit 32. If the result isodd, then "0" will appear in
the32ndbit.
HIGHSPEED
LOWSPEED
DATABITRATEMIN
DATABITRATEMAX
RECEIVERPARITY
RETRIEVINGDATA
Once32validbitsarerecognized,thereceiverlogicgeneratesan
End of Sequence (EOS). If the receiver decoder is enabled and
the 9th and 10th ARINC bits match the control word program bits
or if the receiver decoder is disabled, then EOS clocks the data
readyflagflipfloptoa"1",
or
data flag for a receiver will remain low until after
bytes from that receiver are retrieved. This is accomplished by
activating
with SEL, the byte selector, low to retrieve the first
byte and activating
with SEL high to retrieve the second byte.
retrieves data from receiver 1 and
receiver2.
(orboth)willgo low. The
both
ARINC
retrieves data from
IfanotherARINCwordisreceived,andanewEOSoccursbefore
the two bytes are retrieved, the data is overwritten by the new
word.
D/R1
D/R2
EN
EN
ENI
EN2
SEL
EN
D/R
DEBITS
/
CMUX
CLATCH
32 TO 16 DRIVER
32 BIT LATCH
32 BIT SHIFT REGISTER
TO PINS
BIT BD14
CLOCK
CLOCK
CLK
CAND
SEND OF
PARITY
BIT
DATA
BIT CLOCK
EOS
WORD GAP
WTIMER
BIT CLOCK
END
START
CONTROL
ERROR
CLOCK
DERROR
SHIFT REGISTER
SHIFT REGISTER
NULL
ZEROS
SHIFT REGISTER
ONES
EOS
BITS 9 & 10
FIGURE 2.
RECEIVER BLOCK DIAGRAM
HOLT INTEGRATED CIRCUITS
4
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