- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371816 > HI-5700 (Intersil Corporation) 64 MACROCELL 3.3 VOLT ISP CPLD - NOT RECOMMENDED for NEW DESIGN PDF資料下載
參數(shù)資料
| 型號： | HI-5700 |
| 廠商： | Intersil Corporation |
| 英文描述： | 64 MACROCELL 3.3 VOLT ISP CPLD - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | 8位，20 MSPS的閃光的A / D轉(zhuǎn)換器 |
| 文件頁數(shù)： | 4/12頁 |
| 文件大小： | 746K |
| 代理商： | HI-5700 |
4-1494
Specifications HI-5700
ANALOG INPUTS
Analog Input Resistance, R
IN
Analog Input Capacitance, C
IN
Analog Input Bias Current, IB
V
IN
= 4V
V
IN
= 0V
V
IN
= 0V, 4V
4
-
-
10
60
±
0.01
-
-
±
1.0
-
-
-
-
-
±
1.0
M
pF
μ
A
REFERENCE INPUTS
Total Reference Resistance, R
L
250
330
-
235
-
Reference Resistance Tempco, T
C
-
+0.31
-
-
-
/
°
C
DIGITAL INPUTS
Input Logic High Voltage, V
IH
Input Logic Low Voltage, V
IL
Input Logic High Current, I
IH
Input Logic Low Current, I
IL
Input Capacitance, C
IN
V
IN
= 5V
V
IN
= 0V
2.0
-
-
-
-
-
-
-
-
7
-
0.8
1.0
1.0
-
2.0
-
-
-
-
-
0.8
1.0
1.0
-
V
V
μ
A
μ
A
pF
DIGITAL OUTPUTS
Output Logic Sink Current, I
OL
Output Logic Source Current, I
OH
Output Leakage, I
OZ
Output Capacitance, C
OUT
V
O
= 0.4V
V
O
= 4.5V
CE2 = 0V, V
O
= 0V, 5V
CE2 = 0V
3.2
-
3.2
-
-
-
-
-
5.0
-
-
±
1.0
-
3.2
-
3.2
-
-
-
-
±
1.0
-
mA
mA
μ
A
pF
TIMING CHARACTERISTICS
Aperture Delay, t
AP
Aperture Jitter, t
AJ
Data Output Enable Time, t
EN
Data Output Disable Time, t
DIS
Data Output Delay, t
OD
Data Output Hold, t
H
-
-
-
-
-
10
6
30
18
15
20
20
-
-
25
20
25
-
-
-
-
-
-
5
-
-
30
25
30
-
ns
ps
ns
ns
ns
ns
POWER SUPPLY REJECTION
Offset Error PSRR,
VOS
Gain Error PSRR,
FSE
V
DD
= 5V
±
10%
V
DD
= 5V
±
10%
-
-
±
0.1
±
0.1
±
2.75
±
2.75
-
-
±
5.0
±
5.0
LSB
LSB
POWER SUPPLY CURRENT
Supply Current, I
DD
F
S
= 20MHz
-
145
180
-
190
mA
NOTES:
9. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.
10. Parameter guaranteed by design or characterization and not production tested.
Electrical Specifications
AV
DD
= V
DD
= +5.0V; V
REF+
= +4.0V; V
REF-
= GND = AGND = 0V; F
S
= Specified Clock Frequency at
50% Duty Cycle; C
L
= 30pF; Unless Otherwise Specified
(Continued)
PARAMETER
TEST CONDITION
+25
o
C
(NOTE 2)
0
o
C TO +70
o
C
-
40
o
C TO +85
o
C
UNITS
MIN
TYP
MAX
MIN
MAX
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HI-5700883 | 64 MACROCELL 3.3 VOLT ISP CPLD - NOT RECOMMENDED for NEW DESIGN |
| HI3-5700J-5 | 8-Bit, 20 MSPS Flash A/D Converter |
| HI9P5700J-5 | 8-Bit, 20 MSPS Flash A/D Converter |
| HIF_IOCTL | Using Slow Peripherals with 29K Family Processors Using the HIF ioctl Service for Nonblocking Reads |
| HIF_SPEC | EZ-030 Demonstration Board Theory of Operation Host Interface (HIF) Specification |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HI-5700/883 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:8-Bit, 20 MSPS Flash A/D Converter |
| HI-5700883 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:8-Bit, 20 MSPS Flash A/D Converter |
| HI-5701 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:6-Bit, 30MSPS, Flash A/D Converter |
| HI-5701/883 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:6-Bit, 30 MSPS Flash A/D Converter |
| HI-5701_05 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:6-Bit, 30MSPS, Flash A/D Converter |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。