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參數(shù)資料
| 型號： | HI-518 |
| 廠商： | Intersil Corporation |
| 英文描述： | 64 MACROCELL 3.3 VOLT ISP CPLD - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | 8-Channel/Differential 4通道，高速的CMOS模擬多路復(fù)用器 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大小： | 170K |
| 代理商： | HI-518 |
4
I+, Current
I-, Current
NOTES:
3. V
DD
/LLS pin = open or grounded for TTL compatibility. V
DD
/LLS pin = V
DD
for CMOS compatibility.
4. At temperatures above 90
o
C, care must be taken to assure V
IN
remains at least 1.0V below the V
SUPPLY
for proper operation.
5. V
IN
=
±
10V, I
OUT
= -100
μ
A.
6. V
IN
= 0V, C
L
= 100pF, enable input pulse = 3V, f = 500kHz.
7. C
L
= 40pF, R
L
= 1K, V
EN
= 0.8V, V
IN
= 3V
RMS
, f = 500kHz. Due to the pin to pin capacitance between IN 8/4B and OUT B, channel 8/4B
exhibits 60dB of OFF isolation under the above test conditions.
V
EN
= 2.4V
Full
Full
-
-
-
-
15
15
-
-
-
-
18
18
mA
mA
Electrical Specifications
Supplies = +15V, -15V; V
AH
(Logic Level High) = 2.4V, V
AL
(Logic Level Low) = 0.8V; V
DD
/LLS = GND
(Note 3), Unless Otherwise Specified
(Continued)
PARAMETER
TEST
CONDITIONS
TEMP
(
o
C)
-8
-5
TYP
UNITS
MIN
TYP
MAX
MIN
MAX
Test Circuits and Waveforms
V
DD
/LLS = GND, Unless Otherwise Specified
FIGURE 1. ON RESISTANCE TEST CIRCUIT
FIGURE 2. I
D(OFF)
TEST CIRCUIT
(NOTE 8)
FIGURE 3. I
S(OFF)
TEST CIRCUIT
(NOTE 8)
FIGURE 4. I
D(ON)
TEST CIRCUIT
(NOTE 8)
FIGURE 5A. MEASUREMENT POINTS
FIGURE 5B. TEST CIRCUIT
FIGURE 5. ACCESS TIME
NOTE:
8. Two measurements per channel:
±
10V and 10V. (Two measurements per device for I
D(OFF)
±
10V and 10V.)
OUT
IN
V
IN
V
2
I
OUT
100
μ
A
r
ON
=
V
2
100
μ
A
±
10V
OUT
±
10V
EN
0.8V
10V
A I
D(OFF)
±
OUT
EN
±
10V
A
I
S(OFF)
0.8V
10V
±
OUT
±
10V
EN
2.4V
10V
A
I
D(ON)
±
A
2
A
0
50%
3.5V
10%
+10V
0V
OUTPUT
-10V
t
A
ADDRESS
DRIVE (V
A
)
±
10V
+15V
V+
V-
IN 1
IN 2-7
IN 8
OUTA
OUTB
A
0
EN
V
DD
/LLS
A
1
10
k
50
pF
-15V
A
2
/SDS
50
V
A
2.4V
GND
10V
±
HI-518
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