參數(shù)資料
型號： HI-516
廠商： Intersil Corporation
英文描述： 69 MACROCELL 3.3 VOLT ISP CPLD - NOT RECOMMENDED for NEW DESIGN
中文描述： 16-Channel/Differential 8通道，高速的CMOS模擬多路復(fù)用器
文件頁數(shù)： 4/8頁
文件大?。?/td> 516K
代理商： HI-516
4
Absolute Maximum Ratings
Thermal Information
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33V
Analog Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V
IN
,V
OUT
)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V-) -2V to (V+) +2V
Digital Input Voltage:
TTL Levels Selected (V
DD
/LLS Pin = GND or Open)
V
A0-2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6V to +6V
V
A3/SDS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V-) -2V to (V+) +2V
CMOS Levels Selected (V
DD
/LLS Pin = V
DD
)
V
A0-3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2V to (V+) +2V
Operating Conditions
Temperature Ranges
HI-516-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0
o
C to 75
o
C
Thermal Resistance (Typical, Note 2)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
o
C
Maximum Storage Temperature Range. . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300
o
C
θ
JA
(
o
C/W)
60
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
2.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
Supplies = +15V, -15V; V
AH
(Logic Level High) = 2.4V, V
AL
(Logic Level Low) = 0.8V;
V
DD
/LLS = GND. (Note 3) Unless Otherwise Specified
PARAMETER
TEST
CONDITIONS
TEMP
(
o
C)
-5
UNITS
MIN
TYP
MAX
DYNAMIC CHARACTERISTICS
Access Time, t
A
25
-
130
175
ns
Full
-
-
225
ns
Break-Before-Make Delay, t
OPEN
25
10
20
-
ns
Enable Delay (ON), t
ON(EN)
25
-
120
175
ns
Enable Delay (OFF), t
OFF(EN)
25
-
140
175
ns
Settling Time
To 0.1%
25
-
250
-
ns
To 0.01%
25
-
800
-
ns
Charge Injection Error
Note 6
25
-
-
20
mV
Off Isolation
Note 7
25
55
-
-
dB
Channel Input Capacitance, C
S(OFF)
25
-
-
10
pF
Channel Output Capacitance,
C
D(OFF)
25
-
-
25
pF
Digital Input Capacitance, C
A
25
-
-
10
pF
Input to Output Capacitance,
C
DS(OFF)
25
-
0.02
-
pF
DIGITAL INPUT CHARACTERISTICS
Input Low Threshold, V
AL
(TTL)
Note 3
Full
-
-
0.8
V
Input High Threshold, V
AH
(TTL)
Note 3
Full
2.4
-
-
V
Input Low Threshold, V
AL
(CMOS)
Note 3
Full
-
-
0.3V
DD
V
Input High Threshold, V
AH
(CMOS)
Note 3
Full
0.7V
DD
-
-
V
Input Leakage Current, I
AH
(High)
Full
-
-
1
μ
A
HI-516
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