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參數(shù)資料
| 型號： | HI-509A |
| 廠商： | Intersil Corporation |
| 英文描述： | 16-Channel, 8-Channel, Differential 8-Channel and Differential 4-Channel, CMOS Analog MUXs with Active Overvoltage Protection |
| 中文描述： | 故障保護模擬多路復用器 |
| 文件頁數(shù)： | 7/15頁 |
| 文件大?。?/td> | 235K |
| 代理商： | HI-509A |
7
Absolute Maximum Ratings
Thermal Information
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +44V
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +22V
V- to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25V
Digital Input Voltage (V
EN
, V
A
) . . . . . . . . . . . . . (V-) -4V to (V+) +4V
or 20mA, Whichever Occurs First
Analog Signal (V
IN
, V
OUT
). . . . . . . . . . . . . . . (V-) -20V to (V+) +20V
Continuous Current, IN or OUT . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Peak Current, IN or OUT, Pulsed 1ms, 10% Duty Cycle (Max). . 40mA
Operating Conditions
Temperature Ranges
HI-506A/507A/508A/509A-2, -8 . . . . . . . . . . . . . . -55
o
C to 125
o
C
HI-506A/507A/508A/509A-5, -7 . . . . . . . . . . . . . . . . .0
o
C to 75
o
C
Thermal Resistance (Typical, Note 1)
28 Ld CERDIP Package. . . . . . . . . . . .
16 Ld CERDIP Package. . . . . . . . . . . .
28 Ld PDIP Package . . . . . . . . . . . . . .
16 Ld PDIP Package . . . . . . . . . . . . . .
Maximum Junction Temperature
CERDIP Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
o
C
PDIP Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
o
C
Maximum Storage Temperature Range. . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300
o
C
θ
JA
(
o
C/W)
55
85
60
90
θ
JC
(
o
C/W)
18
32
N/A
N/A
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
Supplies = +15V, -15V; V
REF
Pin = Open; V
AH
(Logic Level High) = 4V; V
AL
(Logic Level Low) = 0.8V,
Unless Otherwise Specified. For Test Conditions, Consult Test Circuits Section
PARAMETER
TEST
CONDITIONS
TEMP
(
o
C)
-2, -8
-5, -7
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
DYNAMIC CHARACTERISTICS
Access Time, t
A
Note 2
25
-
0.5
-
-
0.5
-
μ
s
Full
-
-
1.0
-
-
1.0
μ
s
Break-Before-Make Delay, t
OPEN
Note 2
25
25
80
-
25
80
-
ns
Enable Delay (ON), t
ON(EN)
Note 2
25
-
300
500
-
300
-
ns
Full
-
-
1000
-
-
1000
ns
Enable Delay (OFF), t
OFF(EN)
Note 2
25
-
300
500
-
300
-
ns
Full
-
-
1000
-
-
1000
ns
Settling Time, t
S
HI-506A and HI-507A
To 0.1%
25
-
1.2
-
-
1.2
-
μ
s
To 0.01%
25
-
3.5
-
-
3.5
-
μ
s
HI-508A and HI-509A
To 0.1%
25
-
1.2
-
-
1.2
-
μ
s
To 0.01%
25
-
3.5
-
-
3.5
-
μ
s
Off Isolation
Note 7
25
50
68
-
50
68
-
dB
Channel Input Capacitance, C
S(OFF)
25
-
10
-
-
10
-
pF
Channel Output Capacitance, C
D(OFF)
HI-506A
25
-
52
-
-
52
-
pF
HI-507A
25
-
30
-
-
30
-
pF
HI-508A
25
-
25
-
-
25
-
pF
HI-509A
25
-
12
-
-
12
-
pF
Digital Input Capacitance, C
A
25
-
10
-
-
10
-
pF
Input to Output Capacitance, C
DS(OFF)
25
-
0.1
-
-
0.1
-
pF
DIGITAL INPUT CHARACTERISTICS
Input Low Threshold, TTL Drive, V
AL
Note 2
Full
-
-
0.8
-
-
0.8
V
Input High Threshold, V
AH
(Note 9)
Note 2
Full
4.0
-
-
4.0
-
-
V
Input Leakage Current (High or Low), I
A
Notes 2, 6
Full
-
-
1.0
-
-
1.0
μ
A
HI-506A, HI-507A, HI-508A, HI-509A
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