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參數(shù)資料
| 型號： | HI-3584PQIF-10 |
| 廠商： | HOLT INTEGRATED CIRCUITS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Enhanced ARINC 429 3.3V Serial Transmitter and Dual Receiver |
| 中文描述： | 1 CHANNEL(S), 125K bps, SERIAL COMM CONTROLLER, PQFP52 |
| 封裝： | ROHS COMPLIANT, PLASTIC QFP-52 |
| 文件頁數(shù)： | 2/15頁 |
| 文件大小： | 327K |
| 代理商： | HI-3584PQIF-10 |
SIGNAL
VDD
RIN1A
RIN1B
RIN2A
RIN2B
D/R1
FF1
HF1
D/R2
FF2
HF2
FUNCTION
POWER
INPUT
INPUT
INPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
POWER
DESCRIPTION
+3.3V ± % (All three VDD pins on the chip-scale package
5
ARINC receiver 1 positive input
ARINC receiver 1 negative input
ARINC receiver 2 positive input
ARINC receiver 2 negative input
Receiver 1 data ready flag
FIFO full Receiver 1
FIFO Half full, Receiver 1
Receiver 2 data ready flag
FIFO full Receiver 2
FIFO Half full, Receiver 2
Receiver data byte selection (0 = BYTE 1) (1 = BYTE 2)
Data Bus control, enables receiver 1 data to outputs
Data Bus control, enables receiver 2 data to outputs if
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
0 V
be connect to the same supply)
BD05
BD04
BD03
BD02
BD01
BD00
PL1
PL2
I/O
I/O
I/O
I/O
I/O
I/O
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Latch enable for byte 1 entered from data bus to transmitter FIFO.
Latch enable for byte 2 entered from data bus to transmitter FIFO. Must follow
Transmitter ready flag. Goes low when ARINC word loaded into FIFO. Goes high after
transmission and FIFO empty.
Transmitter FIFO Half Full
Transmitter FIFO Full
“ONES” data output from transmitter
“ZEROS” data output from transmitter
Enable Transmission
Clock for control word register
Read Status Register if SEL=0, read Control Register if SEL=1
Master Clock input
Transmitter Clock equal to Master Clock (CLK), divided by either 10 or 80.
Master Reset, active low
must
SEL
EN1
EN2
is high
BD15
BD14
BD13
BD12
BD11
BD10
BD09
BD08
BD07
BD06
GND
INPUT
INPUT
OUTPUT
TX/R
OUTPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
INPUT
OUTPUT
INPUT
429DO
429DO
ENTX
CWSTR
RSR
CLK
TX CLK
MR
EN1
PL1.
HFT
FFT
PIN DESCRIPTIONS
HOLT INTEGRATED CIRCUITS
2
HI-3584
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HI-3584PQT | Enhanced ARINC 429 3.3V Serial Transmitter and Dual Receiver |
| HI-3584PQT-10 | Enhanced ARINC 429 3.3V Serial Transmitter and Dual Receiver |
| HI-3584PQTF | Enhanced ARINC 429 3.3V Serial Transmitter and Dual Receiver |
| HI-3584PQTF-10 | Enhanced ARINC 429 3.3V Serial Transmitter and Dual Receiver |
| HI-390 | CMOS Analog Switch |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HI-3584PQT | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:Enhanced ARINC 429 3.3V Serial Transmitter and Dual Receiver |
| HI-3584PQT-10 | 制造商:Holt Integrated Circuits 功能描述: |
| HI-3584PQTF | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:Enhanced ARINC 429 3.3V Serial Transmitter and Dual Receiver |
| HI-3584PQTF-10 | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:Enhanced ARINC 429 3.3V Serial Transmitter and Dual Receiver |
| HI-3585 | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:ARINC 429 May 2009 Terminal IC with SPI Interface |
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