參數(shù)資料
型號(hào): HI-3282PJIF
廠商: HOLT INTEGRATED CIRCUITS INC
元件分類: 微控制器/微處理器
英文描述: ARINC 429 SERIAL TRANSMITTER AND DUAL RECEIVER
中文描述: 1 CHANNEL(S), 100K bps, SERIAL COMM CONTROLLER, PQCC44
封裝: ROHS COMPLIANT, PLASTIC, LCC-44
文件頁數(shù): 4/13頁
文件大小: 142K
代理商: HI-3282PJIF
RECEIVER LOGICOPERATION
BIT TIMING
Figure 2 shows a block diagram of the logic section of each
receiver.
The ARINC 429 specification contains the following timing
specification for the received data:
100K BPS ± 1% 12K -14.5K BPS
1.5 ± 0.5 μsec
1.5 ± 0.5 μsec
5 μsec ± 5%
10 ± 5 μsec
10 ± 5 μsec
34.5 to 41.7 μsec
BIT RATE
PULSE RISE TIME
PULSE FALL TIME
PULSE WIDTH
HIGH SPEED
LOW SPEED
RECEIVER PARITY
The receiver parity circuit counts Ones received, including the
parity bit, ARINC bit 32. If the result is odd, then "0" will appear in
the 32nd bit.
Once 32 valid bits are recognized, the receiver logic generates an
End of Sequence (EOS). If the receiver decoder is enabled and
the 9th and 10th ARINC bits match the control word program bits
or if the receiver decoder is disabled, then EOS clocks the data
ready flag flip flop to a "1",
or
data flag for a receiver will remain low until after
from that receiver are retrieved.
activating
with SEL, the byte selector, low to retrieve the first
byte and activating
with SEL high to retrieve the second byte.
EN
(or both) will go low. The
ARINC bytes
This is accomplished by
RETRIEVING DATA
D/R1
D/R2
EN
both
FUNCTIONAL DESCRIPTION (cont.)
SEL
EN
D/R
DECODER
CONTROL
BITS
/
CMUX
LATCH
ENABLE
32 TO 16 DRIVER
32 BIT LATCH
32 BIT SHIFT REGISTER
TO PINS
CONTROL
BIT BD14
CLOCK
CLOCK
CLK
CAND
SEND OF
PARITY
CHECK
32ND
BIT
DATA
BIT CLOCK
EOS
WORD GAP
WORD GAP
TIMER
BIT CLOCK
END
START
SEQUENCE
CONTROL
ERROR
CLOCK
DERROR
SHIFT REGISTER
SHIFT REGISTER
NULL
ZEROS
SHIFT REGISTER
ONES
EOS
BITS 9 & 10
FIGURE 2.
RECEIVER BLOCK DIAGRAM
HI-3282
EN1
receiver 2.
EN2
retrieves data from receiver 1 and
retrieves data from
If another ARINC word is received and a new EOS occurs before
the two bytes are retrieved, the data is overwritten by the new
word.
INTERNAL LIGHTNING PROTECTION (-10 Only)
APPLICATION NOTE 300
The HI-3282-10 configurations are similar to the HI-3282 except
that the ARINC inputs are internally lightning protected to
DO-160D, Level 3 through 10 Kohm resistors that
connected in series with each input from theARINC bus.
be
The design of the HI-3282-10 device requires the external
10 Kohm series resistors for proper ARINC level detection. The
typical 10 volt differential signal is translated and input to a
window comparator and latch. The comparator levels are set so
that, with the external 10 Kohm resistors, they are just below the
standard 6.5 V minimum ARINC data threshold and just above the
2.5 V maximumARINC null threshold.
The receivers of the HI-3282-10 when used with external 10
Kohm resistors will withstand DO-160D, Level 3, waveforms 3, 4
and 5A. No additional lightning protection circuit is necessary.
Please refer to the Holt AN-300 Application Note for additional
information and recommendations on lightning protection of Holt
Line Drivers and Receivers.
must
HOLT INTEGRATED CIRCUITS
4
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