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參數(shù)資料
| 型號(hào)： | HI-3282 |
| 廠商： | Holt Integrated Circuits |
| 英文描述： | ARINC 429 SERIAL TRANSMITTER AND DUAL RECEIVER |
| 中文描述： | ARINC公司429串行發(fā)送器和雙接收機(jī) |
| 文件頁(yè)數(shù)： | 4/13頁(yè) |
| 文件大?。?/td> | 612K |
| 代理商： | HI-3282 |
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RECEIVER LOGICOPERATION
BITTIMING
Figure2showsablockdiagramofthelogicsectionofeach receiver.
The ARINC 429 specification contains the following timing
specificationforthereceiveddata:
100KBPS±1%
1.5±0.5μsec
1.5±0.5μsec
5μsec±5%
12K-14.5KBPS
10±5μsec
10±5μsec
34.5to41.7μsec
BITRATE
PULSERISETIME
PULSEFALLTIME
PULSEWIDTH
HIGHSPEED
LOWSPEED
FUNCTIONAL DESCRIPTION (con't)
The receiver parity circuit counts Ones received, including the
parity bit, ARINC bit 32. If the result is odd, then "0" will appear in
the32ndbit.
RECEIVERPARITY
RETRIEVINGDATA
Once 32 valid bits are recognized, the receiver logic generates
an End of Sequence (EOS). If the receiver decoder is enabled
and the 9th and 10th ARINC bits match the control word
program bits or if the receiver decoder is disabled, then EOS
clocksthedatareadyflagflipfloptoa"1",
will golow. Thedataflagforareceiverwillremain lowuntil after
ARINC bytes from that receiver are retrieved.
accomplished by activating
to retrieve the first byte and activating
retrievethesecondbyte.
retrievesdatafromreceiver1and
retrievesdatafromreceiver2.
EN2
or
(orboth)
This is
with SEL, the byte selector, low
with SEL high to
EN
If another ARINC word is received, and a new EOS occurs
before the twobytes are retrieved,the datais overwrittenbythe
newword.
D/R1
D/R2
EN
ENI
both
SEL
EN
D/R
DEBITS
/
CMUX
CLATCH
32 TO 16 DRIVER
32 BIT LATCH
32 BIT SHIFT REGISTER
TO PINS
BIT BD14
CLOCK
CLOCK
CLK
CAND
SEND OF
PARITY
BIT
DATA
BIT CLOCK
EOS
WORD GAP
WTIMER
BIT CLOCK
END
START
CONTROL
ERROR
CLOCK
DERROR
SHIFT REGISTER
SHIFT REGISTER
NULL
ZEROS
SHIFT REGISTER
ONES
EOS
BITS 9 & 10
FIGURE 2.
RECEIVER BLOCK DIAGRAM
HI-3282
HOLT INTEGRATED CIRCUITS
4
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HI-3282PJI | ARINC 429 SERIAL TRANSMITTER AND DUAL RECEIVER |
| HI-3282PJT | 64 MACROCELL 3.3 VOLT ISP CPLD - NOT RECOMMENDED for NEW DESIGN |
| HI-3282PQI | 64 MACROCELL 3.3 VOLT ISP CPLD - NOT RECOMMENDED for NEW DESIGN |
| HI-3282PQT | ARINC 429 SERIAL TRANSMITTER AND DUAL RECEIVER |
| HI-3282CDI | ARINC 429 SERIAL TRANSMITTER AND DUAL RECEIVER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HI-3282_06 | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:ARINC 429 SERIAL TRANSMITTER AND DUAL RECEIVER |
| HI-3282_13 | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:ARINC 429 Serial Transmitter and Dual Receiver |
| HI-3282B | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:ARINC 429 Serial Transmitter and Dual Receiver |
| HI-3282BPJIF | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:ARINC 429 Serial Transmitter and Dual Receiver |
| HI-3282BPJIF-10 | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:ARINC 429 Serial Transmitter and Dual Receiver |
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