參數(shù)資料
型號: HFCT-5402D
英文描述: 2488 Mb/s Single Mode Fiber Transceiver for SONET OC-48/SDH STM-16 and ATM(應用于SONET OC-48/SDH STM-16 和ATM的2488 Mb/s 單模式光收發(fā)器)
中文描述: 2488 Mb / s的掃描隧道顯微鏡的SONET OC-48/SDH單模光纖收發(fā)器- 16和ATM(應用于的SONET OC-48/SDH的STM - 16和自動柜員機的2488 Mb / s的單模式光收發(fā)器)
文件頁數(shù): 11/20頁
文件大?。?/td> 1017K
代理商: HFCT-5402D
11
1
JP4
1
JP9
C3
100 N
V
CCR
V
CCR
V
EE
L1 10 uH
C4
100 N
C9
10 uF
+
C2
100 N
JP1
1
V
TD+
TD-
V
CCT
V
CCR
SD
RD-
RD+
V
EE
U1
HFCT-5402D
V
CCT
V
CCR
JP7
C12
NOT
FITTED
JP11
1
1
JP12
1
JP13
SW1
SW-SPDT
R1
510 R
V
CCT
R2
3K6
LED1
V
CC
1
O/P
7
GND
8
NC
14
CO1
PECL OSCILLATOR
C13
IN
C11
10 uF
1
JP16
V
CC
_Ck
L3 10 uH
V
CC
_Ck
TD
SD
RD
Clk
Ref
Clk
DNC
L
MON
(+)
L
MON
(-)
BER Signal
R3
510 R
50 ohm test track
TD
C1
100 N
JP2
JP17
JP18
JP3
RD
10
11
12
13
14
15
16
17
18
9
8
7
6
5
4
3
2
1
DNC
V
EE
T
DIS
L
MON+
L
CLK+
CLK-
V
EE
REF CLK
JP10
Clk
JP8
+
C7
100 N
JP5
JP6
C8
100 N
1
JP15
C5
100 N
V
CCT
V
CCT
L2 10 uH
C6
100 N
C10
10 uF
+
Figure 20. Circuit Schematic for the Evaluation Board
Application
Considerations
PCB Layout
Like all RF applications, the PCB
design and layout for this high
speed transceiver requires careful
consideration and attention
towards interconnect impedances
for DATA and CLOCK nodes. Any
form of power supply filtering or
decoupling should be done as
close as possible to the power
supply pins to minimize radiated
or conductive pickup.
It is recommended that high speed
data and clock tracks be buried
striplines to minimize exposure of
these lines for EMI suppression.
Also, such an approach will
ensure signal integrity and avoid
waveform degradation from RF
interference. Plated through holes
or vias used should be as small as
possible to avoid impedance
discontinuities along
interconnecting tracks. Where AC
coupling capacitors are required,
small 0603 size components are
recommended for minimizing
variations in track impedances.
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