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參數(shù)資料
| 型號(hào)： | HFCT-5208 |
| 英文描述： | SC Duplex Single Mode(SC雙工單模式收發(fā)器) |
| 中文描述： | SC雙工單模（南卡羅來雙工單模式收發(fā)器） |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 124K |
| 代理商： | HFCT-5208 |
3
Functional Description
Receiver Section
Design
The receiver section contains an
InGaAs/InP photo detector and a
preamplifier within the
receptacle, coupled to a postamp/
decision circuit on a separate
circuit board.
The postamplifier is ac coupled to
the preamplifier as illustrated in
Figure 1. The coupling capacitor
is large enough to pass the
SONET/SDH test pattern at 622
MBd without significant distor-
tion or performance penalty. If a
lower signal rate, or a code which
has significantly more low
frequency content is used,
sensitivity, jitter and pulse
distortion could be degraded.
Figure 1 also shows a filter net-
work which limits the bandwidth
of the preamp output signal. The
filter is designed to bandlimit the
preamp output noise and thus
improve the receiver sensitivity.
These components will also
reduce the sensitivity of the
receiver as the signal bit rate is
increased above 622 MBd.
Noise Immunity
The receiver includes internal
circuit components to filter
power supply noise. Under some
conditions of EMI and power
supply noise, external power
supply filtering may be necessary.
If receiver sensitivity is found to
be degraded by power supply
noise, the filter network illus-
trated in Figure 2 may be used to
improve performance. The values
of the filter components are
general recommendations and
may be changed to suit a
particular system environment.
Shielded inductors are
recommended.
Terminating the Outputs
The PECL Data outputs of the
receiver may be terminated with
the standard Thevenin-equivalent
50 ohm to V
CC
-2 V termination.
Other standard PECL terminating
techniques may be used.
The two outputs of the receiver
should be terminated with
identical load circuits to avoid
unnecessarily large ac current in
V
CC
. If the outputs are loaded
identically, the ac current is
largely nulled. The SD output of
the receiver is PECL logic and
must be loaded if it is to be used.
The signal detect circuit is much
slower than the data path, so the
ac noise generated by an
asymmetrical load is negligible.
Power consumption may be
reduced by using a higher than
normal load impedance for the
SD output. Transmission line
effects are not generally a
problem as the switching rate is
slow.
The Signal Detect Circuit
The signal detect circuit works by
sensing the peak level of the
received signal and comparing
this level to a reference.
Figure 1. Receiver Block Diagram.
TRANSIMPEDANCE
PREAMPLIFIER
LIMITING
AMPLIFIER
RECEIVER
RECEPTACLE
GND
FILTER
PECL
OUTPUT
BUFFER
PECL
OUTPUT
BUFFER
DATA OUT
DATA OUT
SD
SIGNAL DETECT
CIRCUIT
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