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參數(shù)資料
| 型號(hào)： | HFCT-5205 |
| 英文描述： | SC Duplex Single Mode Transceiver(SC雙工單模式收發(fā)器) |
| 中文描述： | SC雙工單模收發(fā)器（資深大律師雙工單模式收發(fā)器） |
| 文件頁(yè)數(shù)： | 3/11頁(yè) |
| 文件大?。?/td> | 264K |
| 代理商： | HFCT-5205 |
3
Functional Description
Receiver Section
Design
The receiver section contains an
InGaAs/InP photo detector and a
preamplifier within the receptacle,
coupled to a postamp/decision
circuit on a separate circuit board.
The postamplifier is ac coupled to
the preamplifier as illustrated in
Figure 1. The coupling capacitor
is large enough to pass the
SONET/SDH test pattern at
155 MBd without significant
distortion or performance
penalty. If a lower signal rate, or
a code which has significantly
more low frequency content is
used, sensitivity, jitter and pulse
distortion could be degraded.
Figure 1 also shows a filter
network which limits the
bandwidth of the preamp output
signal. The filter is designed to
bandlimit the preamp output
noise and thus improve the
receiver sensitivity.
These components will also
reduce the sensitivity of the
receiver as the signal bit rate is
increased above 155 MBd.
Noise Immunity
The receiver includes internal
circuit components to filter
power supply noise. Under some
conditions of EMI and power
supply noise, external power
supply filtering may be necessary.
If receiver sensitivity is found to
be degraded by power supply
noise, the filter network
illustrated in Figure 2 may be
used to improve performance.
The values of the filter
components are general
recommendations and may be
changed to suit a particular
system environment. Shielded
inductors are recommended.
Terminating the Outputs
The PECL Data outputs of the
receiver may be terminated with
the standard Thevenin-equivalent
50 ohm to V
CC
- 2 V termination.
Other standard PECL terminating
techniques may be used.
The two outputs of the receiver
should be terminated with
identical load circuits to avoid
unnecessarily large ac current in
V
CC
. If the outputs are loaded
identically the ac current is
largely nulled. The Signal Detect
output of the receiver is PECL
logic and must be loaded if it is to
be used. The Signal Detect
circuit is much slower than the
data path, so the ac noise
generated by an asymmetrical
load is negligible. Power
consumption may be reduced by
using a higher than normal load
impedance for the Signal Detect
output. Transmission line effects
are not generally a problem as the
switching rate is slow.
The Signal Detect Circuit
The Signal Detect circuit works
by sensing the peak level of the
received signal and comparing
this level to a reference.
RECEIVER
RECEPTACLE
TRANS-
IMPEDANCE
PRE-
AMPLIFIER
FILTER
GND
LIMITING
AMPLIFIER
PECL
OUTPUT
BUFFER
PECL
OUTPUT
BUFFER
DATA OUT
SIGNAL
DETECT
CIRCUIT
SD
DATA OUT
Figure 1 - Receiver Block Diagram
Figure 2 - p Filter Network for Noise Filtering
V
CC
10 μF
3.3 μH
100 nF
100 nF
FILTERED V
CC
to DATA LINK
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HFCT-5205A | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:SC Duplex Single Mode Transceiver |
| HFCT-5205B | 制造商:Avago Technologies 功能描述:TRANSCEIVER FIBRE |
| HFCT-5205C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FIBER OPTIC TRANSCEIVER |
| HFCT-5205D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:155 Mb/s SMF Transceiver for SONET/SDH OC-3/SDH STM-1 0C to +70C Blue Case |
| HFCT5207B | 制造商:Hewlett Packard Co 功能描述:Fiber Optic Transceiver |
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