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參數(shù)資料
| 型號： | HFA3841 |
| 廠商： | Intersil Corporation |
| 英文描述： | 288 MACROCELL 3.3 VOLT ISP CPLD |
| 中文描述： | 無線局域網(wǎng)媒體訪問控制器 |
| 文件頁數(shù)： | 22/27頁 |
| 文件大?。?/td> | 211K |
| 代理商： | HFA3841 |
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22
In transmit mode, the HFA386X is used in the mode where it
generates the PLCP header internally and only the MPDU is
passed from HFA3841. In receive, the HFA386X is used in
the mode where it passes the PLCP header and the MPDU
to the HFA3841.
BBP Packet Reception
There are 4 signals associated with the BBP Receive Port:
RX_PE (receive enable), MDRDY (receive ready), RXD
(receive data), and RXCLK (receive clock). These connect to
the HFA3841 on pins PL1, PK5, RXD, and RXC,
respectively.
The receive demodulator in the BBP is activated via RX_PE.
When RX_PE goes active the demodulator scrutinizes I and
Q for packet activity. When a packet arrives at a valid signal
level the demodulator acquires and tracks the incoming
signal. It then sifts through the demodulator data for the Start
Frame Delimiter (SFD). Normally, MDRDY is programmed to
go active after SFD is detected. This signals the HFA3841,
allowing it to pick off the needed header fields from the real-
time demodulated bitstream rather than having to read these
fields through the BBP Control Port.
Assuming all is well with the header, the BBP decodes the
signal field in the header and switches to the appropriate
data rate. If the signal field is not recognized, or the CRC16
is in error, then MDRDY will go inactive shortly after CRC16
and the demodulator will return to acquisition mode looking
for another packet. If all is well with the header, and after the
demodulator has switched to the appropriate data rate, then
the demodulator will continue to provide data to the
HFA3841 indefinitely.
Receive Port exchange details are depicted in Figure 20.
Detailed timing is related in Figure 21 and Table 2.
For more detailed information concerning BBP packet
reception see the HFA386x data sheets.
FIGURE 20. BBP RECEIVE PORT TIMING
LSB
MSB
DATA PACKET
RXC
RX_PE
MDRDY
RXD
HEADER
FIELDS
PROCESSING
PREAMBLE/HEADER
DATA
RX_PE
I
IN
, Q
IN
t
RLP
MDRDY
RXC
RXD
CCA, RSSI
t
CCA
t
RD3
t
RDI
t
RCD
t
RCP
t
REH
t
RD2
FIGURE 21. BBP RECEIVE PORT SIGNAL TIMING
NOTE: RXD, MDRDY is output two MCLK after RXC rising to provide hold time. RSSI output on TEST (5:0).
t
RCD
t
RDD
t
RDS
Preliminary - HFA3841
相關PDF資料 |
PDF描述 |
|---|---|
| HFA3841CN | 288 MACROCELL 3.3 VOLT ISP CPLD |
| HFA3841CN96 | Wireless LAN Medium Access Controller |
| HFA3842A | PCMCIA/USB Wireless LAN Medium Access Controller |
| HFA3842AIN | 3.3V 288-mc CPLD |
| HFA3842AIN-TK | Circular Connector; No. of Contacts:41; Series:MS27473; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:20; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:20-41 RoHS Compliant: No |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HFA3841CN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HFA3841CN96 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Wireless LAN Medium Access Controller |
| HFA3842 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Wireless LAN Medium Access Controller |
| HFA3842A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:PCMCIA/USB Wireless LAN Medium Access Controller |
| HFA3842AIN | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:PCMCIA/USB Wireless LAN Medium Access Controller |
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