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參數(shù)資料
| 型號： | HFA1110IB |
| 廠商： | INTERSIL CORP |
| 元件分類： | 運動控制電子 |
| 英文描述： | 750MHz, Low Distortion Unity Gain, Closed Loop Buffer |
| 中文描述： | BUFFER AMPLIFIER, PDSO8 |
| 封裝： | MS-012AA, SOIC-8 |
| 文件頁數(shù)： | 10/13頁 |
| 文件大?。?/td> | 104K |
| 代理商： | HFA1110IB |
10
HFA1110/883
PC Board Layout
The frequency response of this buffer depends greatly on
the amount of care taken in designing the PC board.
The
use of low inductance components such as chip resis-
tors and chip capacitors is strongly recommended,
while a solid ground plane is a must!
Attention should be given to decoupling the power supplies.
A large value (10
μ
F) tantalum in parallel with a small value
(0.1
μ
F) chip capacitor works well in most cases.
Terminated microstrip signal lines are recommended at the
input and output of the device. Capacitance directly on the
output must be minimized, or isolated as discussed in the
next section. Removing the GND plane under the output
trace helps minimize this capacitance.
An example of a good high frequency layout is the Evalua-
tion Board shown in Figure 25.
Driving Capacitive Loads
Capacitive loads, such as an A/D input, or an improperly
terminated transmission line will degrade the buffer’s phase
margin resulting in frequency response peaking and possi-
ble oscillations. In most cases, the oscillation can be avoided
by placing a resistor (R
S
) in series with the output prior to
the capacitance.
Figure 24 details starting points for the selection of this resis-
tor. The points on the curve indicate the R
S
and C
L
combina-
tions for the optimum bandwidth, stability, and settling time,
but experimental fine tuning is recommended. Picking a
point above or to the right of the curve yields an overdamped
response, while points below or left of the curve indicate
areas of underdamped performance.
R
S
and C
L
form a low pass network at the output, thus limit-
ing system bandwidth well below the buffer bandwidth of
750MHz. By decreasing R
S
as C
L
increases (as illustrated in
Figure 24), the maximum bandwidth is obtained without sac-
rificing stability. Even so, bandwidth does decrease as you
move to the right along the curve.
Evaluation Board
The performance of this buffer may be evaluated using the
HFA1110 Evaluation Board. The layout and schematic of the
board are shown in Figure 25.
To order evaluation boards, please contact your local sales
office.
TOP LAYOUT
BOTTOM LAYOUT
R
S
)
LOAD CAPACITANCE (pF)
50
45
40
35
30
25
20
15
10
5
0
0
40
80
120
160
200
240
280
320
360
400
FIGURE 24. RECOMMENDED SERIES OUTPUT RESISTOR vs
LOAD CAPACITANCE
1
50
1
2
3
4
8
7
6
5
+5V
0.1
μ
F
10
μ
F
50
OUT
0.1
μ
F
10
μ
F
-5V
HFA1110
IN
R
S
FIGURE 25. EVALUATION BOARD SCHEMATIC AND LAYOUT
Spec Number
511083-883
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HFA1110EVAL | 750MHz, Low Distortion Unity Gain, Closed Loop Buffer |
| HFA1110 | 750MHz, Low Distortion Unity Gain,Closed Loop Buffer(750MHz,低失真單位增益,閉環(huán)緩沖器) |
| HFA1112 | Ultra High Speed Programmable Gain Buffer Amplifier(超高速可編程增益緩沖器放大器) |
| HFA1113 | 850MHz, Low Distortion, Output Limiting, Programmable Gain, Buffer Amplifier(850MHz、低失真、輸出限定可編程增益緩沖放大器) |
| HFA1115883 | High Speed, Low Power, Output Limiting Closed Loop Buffer Amplifier |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HFA1110IBZ | 功能描述:運算放大器 - 運放 BUFR 750MHZ CFB UNITY-GAIN IND RoHS:否 制造商:STMicroelectronics 通道數(shù)量:4 共模抑制比（最小值）:63 dB 輸入補償電壓:1 mV 輸入偏流（最大值）:10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-16 轉(zhuǎn)換速度:0.89 V/us 關(guān)閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel |
| HFA1110IJ | 制造商:Harris Corporation 功能描述: |
| HFA1110IP | 制造商:Rochester Electronics LLC 功能描述:850MHZ UNITY GAIN BUFFER,8 PIN PDIP - Bulk |
| HFA1110MJ/883 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HFA1112 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:850MHz, Low Distortion Programmable Gain Buffer Amplifier |
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