參數(shù)資料
型號(hào): HEF4516B
廠商: NXP Semiconductors N.V.
元件分類: 通用總線功能
英文描述: Binary up/down counter(二進(jìn)制加/減計(jì)數(shù)器)
中文描述: 二進(jìn)制加/減計(jì)數(shù)器(二進(jìn)制加/減計(jì)數(shù)器)
文件頁數(shù): 2/10頁
文件大?。?/td> 129K
代理商: HEF4516B
January 1995
2
Philips Semiconductors
Product specification
Binary up/down counter
HEF4516B
MSI
DESCRIPTION
The HEF4516B is an edge-triggered synchronous
up/down 4-bit binary counter with a clock input (CP), an
up/down count control input (UP/DN), an active LOW
count enable input (CE), an asynchronous active HIGH
parallel load input (PL), four parallel inputs (P
0
to P
3
), four
parallel outputs (O
0
to O
3
), an active LOW terminal count
output (TC), and an overriding asynchronous master reset
input (MR).
Information on P
0
to P
3
is loaded into the counter while PL
is HIGH, independent of all other input conditions except
MR which must be LOW. When PL and CE are LOW, the
counter changes on the LOW to HIGH transition of CP.
Input UP/DN determines the direction of the count, HIGH
for counting up, LOW for counting down. When counting
up,TC is LOW when O
0
and O
3
are HIGH andCE is LOW.
When counting down, TC is LOW when O
0
to O
3
and
CE are LOW. A HIGH on MR resets the counter (O
0
to
O
3
= LOW) independent of all other input conditions.
Fig.1 Functional diagram.
HEF4516BP(N):
HEF4516BD(F):
HEF4516BT(D):
( ): Package Designator North America
16-lead DIL; plastic (SOT38-1)
16-lead DIL; ceramic (cerdip) (SOT74)
16-lead SO; plastic (SOT109-1)
Fig.2 Pinning diagram.
PINNING
FAMILY DATA, I
DD
LIMITS category MSI
See Family Specifications
PL
P
0
to P
3
CE
CP
parallel load input (active HIGH)
parallel inputs
count enable input (active LOW)
clock pulse input (LOW to HIGH,
edge triggered)
up/down count control input
master reset input
terminal count output (active LOW)
parallel outputs
UP/DN
MR
TC
O
0
to O
3
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