參數(shù)資料
型號: HEF4060BT,653
廠商: NXP Semiconductors
文件頁數(shù): 2/7頁
文件大?。?/td> 0K
描述: IC BNRY COUNT/DVDER 14STG 16SOIC
產(chǎn)品培訓(xùn)模塊: Logic Packages
標(biāo)準(zhǔn)包裝: 1
系列: 4000B
邏輯類型: 二進(jìn)制計數(shù)器
方向:
元件數(shù): 1
每個元件的位元數(shù): 14
復(fù)位: 異步
計數(shù)速率: 30MHz
觸發(fā)器類型: 負(fù)邊沿
電源電壓: 4.5 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-SO
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: 568-8236-6
January 1995
2
Philips Semiconductors
Product specication
14-stage ripple-carry binary
counter/divider and oscillator
HEF4060B
MSI
DESCRIPTION
The HEF4060B is a 14-stage ripple-carry binary
counter/divider and oscillator with three oscillator terminals
(RS, RTC and CTC), ten buffered outputs (O3 to O9 and
O11 to O13) and an overriding asynchronous master reset
input (MR). The oscillator configuration allows design of
either RC or crystal oscillator circuits. The oscillator may
be replaced by an external clock signal at input RS. The
counter advances on the negative-going transition of RS.
A HIGH level on MR resets the counter (O3 to O9 and
O11 to O13 = LOW), independent of other input conditions.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
Fig.1 Functional diagram.
Fig.2 Pinning diagram.
PINNING
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
MR
master reset
RS
clock input/oscillator pin
RTC
oscillator pin
CTC
external capacitor connection
O3 to O9
counter outputs
O11 to O13
HEF4060BP(N):
16-lead DIL; plastic (SOT38-1)
HEF4060BD(F):
16-lead DIL; ceramic (cerdip) (SOT74)
HEF4060BT(D):
16-lead SO; plastic (SOT109-1)
( ): Package Designator North America
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