- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄2034 > HEF4059BT,653 (NXP Semiconductors)IC PROG DIV-BY-N COUNTER 24SOIC PDF資料下載
參數(shù)資料
| 型號(hào)： | HEF4059BT,653 |
| 廠商： | NXP Semiconductors |
| 文件頁(yè)數(shù)： | 4/6頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PROG DIV-BY-N COUNTER 24SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Logic Packages |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | 4000B |
| 邏輯類型： | 除以 N |
| 方向： | 下 |
| 元件數(shù)： | 1 |
| 每個(gè)元件的位元數(shù)： | 16 |
| 復(fù)位： | 異步 |
| 計(jì)數(shù)速率： | 20MHz |
| 觸發(fā)器類型： | 正邊沿 |
| 電源電壓： | 4.5 V ~ 15.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SO |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 933645510653 HEF4059BT-T HEF4059BT-T-ND |
January 1995
4
Philips Semiconductors
Product specication
Programmable divide-by-n counter
HEF4059B
LSI
Figure 3 illustrates the operation of the counter in mode
÷ 8 starting from the preset state 3.
Fig.3 Total count of 3.
CP INPUT
Kc INPUT
(Ka, Kb = LOW)
internal state
of counter
O OUTPUT
If the ‘master preset’ mode is started two clock cycles or
less before an output pulse, the output pulse will appear at
the time due. If the ‘master preset’ mode is not used the
counter is preset in accordance with the ‘jam inputs when
the output pulse appears. A HIGH level at the latch enable
input (EL) will cause the counter output to go HIGH once
an output pulse occurs, and remain in the HIGH state until
EL input returns to LOW. If the EL input is LOW, the output
pulse will remain HIGH for only one cycle of the clock input
signal.
When Ka = L, Kb = H, Kc = L and EL = L, the counter
operates in the ‘preset inhibit’ mode, with which the
dividend of the counter is fixed to 10 000, independent of
the state of the jam inputs.
When in the same state of mode select inputs EL = H, the
counter operates in the normal
÷ 10 mode, however,
without the latch operation at the output.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HGC1M-EC | HEEL GROUNDER ASSY ECONOMY W/RES |
| HGC1M-N72-BLU | ESD HEEL GROUNDER BLUE CUP STYLE |
| IDT74ALVC16835PFG8 | IC UNIV BUS DVR 18BIT 56TVSOP |
| IDT74ALVCF162835APFG | IC UNIV BUS DVR 18BIT 56TVSOP |
| IDT74ALVCH162373PVG | IC XPARENT LATCH 16BIT D 48-SSOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HEF4059BTD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Prescaler/Frequency Divider |
| HEF4059BTD-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Prescaler/Frequency Divider |
| HEF4059BT-T | 功能描述:計(jì)數(shù)器移位寄存器 PROGRMABLE DIVIDE BY N COUNTER RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| HEF4060B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:14-stage ripple-carry binary counter/divider and oscillator |
| HEF4060BD | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:14-stage ripple-carry binary counter/divider and oscillator |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。