參數(shù)資料
型號: HEF40161BT
廠商: NXP SEMICONDUCTORS
元件分類: 通用總線功能
英文描述: 4-bit synchronous binary counter with asynchronous reset
中文描述: 4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16
封裝: PLASTIC, SOT109-1, SO-16
文件頁數(shù): 6/10頁
文件大?。?/td> 152K
代理商: HEF40161BT
January 1995
6
Philips Semiconductors
Product specification
4-bit synchronous binary counter with
asynchronous reset
HEF40161B
MSI
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
= 25
°
C; C
L
= 50 pF; input transition times
20 ns
Output transition times
HIGH to LOW
5
60
30
20
60
30
20
120
60
40
120
60
40
ns
ns
ns
ns
ns
ns
10 ns
+
(1,0 ns/pF) C
L
9 ns
+
(0,42 ns/pF) C
L
6 ns
+
(0,28 ns/pF) C
L
10 ns
+
(1,0 ns/pF) C
L
9 ns
+
(0,42 ns/pF) C
L
6 ns
+
(0,28 ns/pF) C
L
10
15
5
10
15
t
THL
LOW to HIGH
t
TLH
V
DD
V
SYMBOL
MIN.
TYP.
MAX.
Minimum clock
pulse width; LOW
5
100
40
30
100
40
30
25
15
10
110
40
30
120
40
25
260
100
70
20
10
50
20
15
50
20
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
see also waveforms
Figs 5, 6, 7 and 8
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
t
WCPL
Minimum MR
pulse width; LOW
t
WMRL
Recovery time
for MR
0
0
0
t
RMR
Set-up times
P
n
CP
55
20
15
60
20
10
130
50
35
35
10
10
45
15
10
105
35
25
t
su
PE
CP
t
su
CEP, CET
CP
t
su
Hold times
P
n
CP
t
hold
5
15
PE
CP
t
hold
5
5
25
15
10
CEP, CET
CP
t
hold
V
DD
V
SYMBOL
MIN.
TYP.
MAX.
TYPICAL EXTRAPOLATION
FORMULA
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