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| 型號(hào)： | HEC4094BT |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 通用總線功能 |
| 英文描述： | 8-stage shift-an-store register |
| 封裝： | HEC4094BT<SOT109-1 (SO16)|<<http://www.nxp.com/packages/SOT109-1.html<1<week 6, 2004,;HEF4094BP<SOT38-4 (DIP16)|<<http://www.nxp.com/packages/SOT38-4.html<1<Always |
| 文件頁(yè)數(shù)： | 8/19頁(yè) |
| 文件大?。?/td> | 160K |
| 代理商： | HEC4094BT |
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HEF4094B_8
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 08 — 2 April 2010
8 of 19
NXP Semiconductors
HEF4094B
8-stage shift-and-store register
[1]
The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (C
L
in pF).
t
PLZ
LOW to OFF-state
propagation delay
OE to QPn;
see
Figure 8
5 V
10 V
15 V
5 V
10 V
15 V
5 V
10 V
15 V
5 V
10 V
15 V
5 V
10 V
15 V
5 V
10 V
15 V
-
-
-
60
20
15
+5
20
20
60
30
24
40
30
24
5
11
14
80
40
30
30
10
5
15
160
80
60
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
t
su
set-up time
D to CP;
see
Figure 9
t
h
hold time
D to CP;
see
Figure 9
5
5
t
W
pulse width
minimum LOW
clock pulse;
see
Figure 6
30
15
12
20
15
12
10
22
28
minimum HIGH
strobe pulse;
see
Figure 7
f
max
maximum frequency
see
Figure 6
Table 7.
V
SS
= 0 V; T
amb
= 25
°
C; for test circuit see
Figure 10
; unless otherwise specified.
Symbol
Parameter
Conditions
Dynamic characteristics
…continued
V
DD
Extrapolation formula
Min
Typ
Max
Unit
Table 8.
V
SS
= 0 V; t
r
= t
f
≤
20 ns; T
amb
= 25
°
C.
Symbol
Parameter
P
D
dynamic power
dissipation
Dynamic power dissipation
V
DD
5 V
10 V
15 V
Typical formula for P
D
(
μ
W)
P
D
= 2100
×
f
i
+
Σ
(f
o
×
C
L
)
×
V
DD2
P
D
= 9700
×
f
i
+
Σ
(f
o
×
C
L
)
×
V
DD2
P
D
= 26000
×
f
i
+
Σ
(f
o
×
C
L
)
×
V
DD2
where:
f
i
= input frequency in MHz,
f
o
= output frequency in MHz,
C
L
= output load capacitance in pF,
V
DD
= supply voltage in V,
Σ
(f
o
×
C
L
) = sum of the outputs.
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