參數(shù)資料
型號(hào)： HDMP-1636A
英文描述： Gigabit Ethernet Serialize/Deserialize (SerDes) IC(千兆位以太網(wǎng)串行器/解串行器)
中文描述： 千兆以太網(wǎng)序列化/反序列化器（SerDes）集成電路（千兆位以太網(wǎng)串行器/解串行器）
文件頁(yè)數(shù)： 3/16頁(yè)
文件大?。?/td> 248K
代理商： HDMP-1636A
3
For test purposes, the transceiver
provides for on-chip local loop-
back functionality, controlled
through an external input pin.
Additionally, the byte
synchronization feature may be
disabled. This may be useful in
proprietary applications which
use alternative methods to align
the parallel data.
HDMP-1636A/46A/
T1636A Block Diagram
The HDMP-1636A/46A/T1636A
was designed to transmit and
receive 10-bit wide parallel data
over a single high-speed line. The
parallel data applied to the trans-
mitter is expected to be encoded
per the Gigabit Ethernet specifi-
cation, which uses an 8B/10B
encoding scheme with special
reserve characters for link
management purposes. In order
to accomplish this task, the
HDMP-1636A/46A/T1636A
incorporates the following:
TTL Parallel I/Os
High Speed Phase Locked
Loops
Parallel to Serial Converter
High Speed Serial Clock and
Data Recovery Circuitry
Comma Character Recognition
Circuitry as per 8B/10B
Specifications
Byte Alignment Circuitry
Serial to Parallel Converter
INPUT LATCH
The transmitter accepts 10-bit
wide TTL parallel data at inputs
TX[0..9]. The user-provided
reference clock signal, REFCLK,
is also used as the transmit byte
clock. The TX[0..9] and REFCLK
signals must be properly aligned,
as shown in Figure 3.
TX PLL/CLOCK GENERATOR
The transmitter Phase Locked
Loop and Clock Generator (TX
PLL/CLOCK GENERATOR) block
is responsible for generating all
internal clocks needed by the
transmitter section to perform its
functions. These clocks are based
on the supplied reference byte
clock (REFCLK). REFCLK is
used as both the frequency
reference clock for the PLL and
the transmit byte clock for the
incoming data latches. It is
expected to be 125 MHz and
properly aligned to the incoming
parallel data (see Figure 3). This
clock is then multiplied by 10 to
generate the 1250 MHz clock
necessary for clocking the high
speed serial outputs.
FRAME MUX
The FRAME MUX accepts the 10-
bit wide parallel data from the
INPUT LATCH. Using internally
generated high speed clocks, this
parallel data is multiplexed into
the 1250 MBd serial data stream.
The data bits are transmitted
sequentially, from the least
significant bit (TX[0]) to the
most significant bit (TX[9]).
OUTPUT SELECT
The OUTPUT SELECT block
provides for an optional internal
loopback of the high speed serial
signal for testing purposes.
In normal operation, LOOPEN is
set low and the serial data stream
is placed at +/- DOUT. When
wrap-mode is activated by setting
LOOPEN high, the +/- DOUT
pins are held static at logic 1 and
the serial output signal is
internally wrapped to the INPUT
SELECT box of the receiver
section.
INPUT SELECT
The INPUT SELECT block
determines whether the signal at
+/- DIN or the internal loop-back
serial signal is used. In normal
operation, LOOPEN is set low
and the serial data is accepted at
+/- DIN. When LOOPEN is set
high, the high speed serial signal
is internally looped-back from the
transmitter section to the
receiver section. This feature
allows for loop back testing
exclusive of the transmission
medium.
RX PLL/CLOCK RECOVERY
The RX PLL/CLOCK RECOVERY
block is responsible for frequency
and phase locking onto the
incoming serial data stream and
recovering the bit and byte
clocks. An automatic locking
feature allows the Rx PLL to lock
onto the input data stream
without external PLL training
controls. It does this by
continually frequency locking
onto the 125 MHz reference
clock, and then phase locking
onto the input data stream. An
internal signal detection circuit
monitors the presence of the
相關(guān)PDF資料
PDF描述
HDMP-T1636A Gigabit Ethernet Serialize/Deserialize (SerDes) IC(千兆位以太網(wǎng)串行器/解串行器)
HDN1075O Plug-In Relay; Contacts:DPDT; Coil Voltage AC Max:120V; Contact Carry Current:10A; Relay Terminals:8-Pin Octal; Relay Mounting:Plug-In; Contact Carrying Power:2VA; Contact Rating:10A; Mounting Type:Plug In; Switch Function:DPDT
HDN1077O Pressure Transducer, Series 19 mm, Compensated, Pressure Range: 0 psi to 200 psi, Gage, 1/4 BSPP, 10 Vdc excitation
HDN1075 0.28(7MM) SEVEN SEGMANT NUMERIC DISPLAY SOW CURRENT
HDN1075G ; Series:QW; Resistance:10kohm; Resistance Tolerance:+/-2%; Operating Temperature Range:-55 C to +155 C; Resistor Element Material:Metal Oxide; Voltage Rating:250VDC; Temperature Coefficient:+/-200ppm/ C; Package/Case:Axial RoHS Compliant: Yes
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HDMP-1636AG 制造商:PMC-Sierra 功能描述:1.06/1.25 GB SerDes for GB EOL301107
HDMP-1637A 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:1.25 GBd SerDes Circuit with Differential PECL Clock Inputs for Gigabit Ethernet Applications
HDMP-1638 制造商:AGILENT 制造商全稱(chēng):AGILENT 功能描述:Gigabit Ethernet Transceiver Chip with Dual Serial I/O and Differential PECL Clock Inputs
HDMP-1646 制造商:AGILENT 制造商全稱(chēng):AGILENT 功能描述:Gigabit Ethernet Transceiver Chip
HDMP-1646A 制造商:Agilent 功能描述:_
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