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參數(shù)資料
| 型號： | HDMP-1536A |
| 英文描述： | Fibre Channel Transceiver Chip(光纖通道收發(fā)器芯片) |
| 中文描述： | 光纖通道收發(fā)器芯片（光纖通道收發(fā)器芯片） |
| 文件頁數(shù)： | 13/16頁 |
| 文件大小： | 246K |
| 代理商： | HDMP-1536A |
13
TRx I/O Definition (cont’d.)
Name
Pin
RX[0]
RX[1]
RX[2]
RX[3]
RX[4]
RX[5]
RX[6]
RX[7]
RX[8]
RX[9]
RXCAP0
RXCAP1
SIG_DET
Type
O-TTL
Signal
45
44
43
41
40
39
38
36
35
34
48
49
26
Data Outputs:
One 10 bit data byte. RX[0] is the first bit received.
RX[0] is the least significant bit.
C
Loop Filter Capacitor:
A loop filter capacitor for the internal PLL must
be connected across the RXCAP0 and RXCAP1 pins. (typical value = 0.1
μ
F).
Signal Detect:
Indicates a loss of signal on the high-speed differential inputs,
±
DIN, as in the case where the transmission cable becomes disconnected.
If
±
DIN > = 200 mV peak-to-peak, SIG_DET = logic 1.
If
±
DIN < = 200 mV and
±
DIN > 50 mV, SIG_DET = undefined.
If
±
DIN < = 50 mV, SIG_DET = logic 0, RX[0:9] = 1111111111.
Data Inputs:
One, 10 bit, pre-encoded data byte. TX[0] is the first bit
transmitted. TX[0] is the least significant bit.
O-TTL
TX[0]
TX[1]
TX[2]
TX[3]
TX[4]
TX[5]
TX[6]
TX[7]
TX[8]
TX[9]
TXCAP1
TXCAP0
V
CC
2
3
4
6
7
8
9
11
12
13
16
17
I-TTL
C
Loop Filter Capacitor:
A loop filter capacitor must be connected across
the TXCAP1 and TXCAP0 pins (typical value = 0.1
μ
F).
Logic Power Supply:
Normally 3.3 volts. Used for internal receiver
PECL logic. It should be isolated from the noisy TTL supply as well as
possible.
Analog Power Supply:
Normally 3.3 volts. Used to provide a clean
supply line for the PLL and high-speed analog cells.
This pin is bonded to an isolated pad and has no functionality. However,
it is recommended that this pin be connected to V
CC
in order to conform
with the X3T11 “10-bit specification,” and to help dissipate heat.
TTL Power Supply:
Normally 3.3 volts. Used for all TTL receiver output
buffer cells.
20,23
28
57,59
50
S
V
CC
_RXA
S
*V
CC
5
10
S
53,55
29
37
42
18
V
CC
_RXTTL
S
V
CC
_TXA
S
Analog Power Supply:
Normally 3.3 volts. Used to provide a clean
supply line for the PLL and high-speed analog cells.
High-Speed ECL Supply:
Normally 3.3 volts. Used only for the last stage
of the high-speed transmitter output cell (HS_OUT) as shown in
Figure 10. Due to high current transitions, this V
CC
should be well
bypassed to a ground plane.
High-Speed Supply:
Normally 3.3 volts. Used by the transmitter side for the
high-speed circuitry. Noise on this line should be minimized for best operation.
V
CC
_TXECL
60
S
V
CC
_TXHS
63
S
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| HDMP-1636 | Software |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HDMP-1546 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Fibre Channel Transceiver Chip |
| HDMP-1546A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:IC-TRANSCEIVER |
| HDMP-1636 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Gigabit Ethernet Transceiver Chip |
| HDMP-1636A | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Gigabit Ethernet and Fibre Channel SerDes ICs |
| HDMP-1636AG | 制造商:PMC-Sierra 功能描述:1.06/1.25 GB SerDes for GB EOL301107 |
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