參數(shù)資料
型號: HDD64M72D18W-13B
廠商: Hanbit Electronics Co.,Ltd.
英文描述: DDR SDRAM Module 512Mbyte (64Mx72bit), based on 32Mx8, 4Banks, 8K Ref., with 184Pin-DIMM
中文描述: DDR SDRAM內(nèi)存模塊512Mbyte(64Mx72bit),在32Mx8,4Banks,8K的參考依據(jù)。與184Pin - DIMM內(nèi)存
文件頁數(shù): 5/12頁
文件大?。?/td> 190K
代理商: HDD64M72D18W-13B
HANBit
HDD64M72D18W
URL : www.hbe.co.kr 5 HANBit Electronics Co.,Ltd
.
REV 1.0 (August.2002)
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNTE
Voltage on any pin relative to Vss
V
IN
, V
OUT
-0.5 ~ 3.6
V
Voltage on V
DD
supply relative to Vss
V
DD
-1.0 ~ 3.6
V
Voltage on V
DDQ
supply relative to Vss
V
DDQ
-0.5 ~ 3.6
V
Storage temperature
T
STG
-55 ~ +150
°
C
Power dissipation
P
D
27
W
Short circuit current
No
tes:
Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITIONS
I
OS
50
mA
(Recommended operating conditions (Voltage referenced to Vss = 0V, T
A
= 0 to 70
°
C) )
PARAMETER
SYMBOL
MIN
MAX
UNIT
NOTE
Supply Voltage
V
DD
2.3
2.7
V
I/O Supply Voltage
V
DDQ
2.3
2.7
V
I/O Reference Voltage
V
REF
V
DDQ
/2 - 50mA
V
DDQ
/2 +
50mA
V
1
I/O Termination Voltage(system)
V
TT
V
REF
0.04
V
REF
+ 0.04
V
2
Input High Voltage
V
IH
(DC)
V
REF
+ 0.15
V
REF
+ 0.3
V
4
Input Low Voltage
V
IL
(DC)
-0.3
V
REF
- 0.15
V
4
Input Voltage Level, CK and /CK inputs
V
IN
(DC)
-0.3
V
DDQ
+ 0.3
V
Input Differential Voltage, CK and /CK inputs
V
ID
(DC)
0.3
V
DDQ
+ 0.6
V
3
Input crossing point Voltage, CK and /CK
inputs
V
IX
(DC)
1.15
1.35
V
5
Input leakage current
I
LI
-2
2
uA
Output leakage current
I
OZ
-5
5
uA
Output High current (V
OUT
= 1.95V)
I
OH
-16.8
mA
Output Low current (V
OUT
= 0.35V)
I
OL
16.8
mA
Notes :
1. Includes
±
25mV margin for DC offset on V
REF
, and a combined total of
±
50mV margin for all AC noise and DC
offset on V
REF
, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on V
REF
and
internal DRAM noise coupled to V
REF
, both of which may result in V
REF
noise. V
REF
should be de-coupled with an
inductance of
3nH.
2. V
TT
is not applied directly to the device. V
TT
is a system supply for signal termination resistors, is expected to be set
equal to V
REF
, and must track variations in the DC level of V
REF
3. V
ID
is the magnitude of the difference between the input level on CK and the input level on CK.
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the
pad in simulation. The AC and DC input specifications are relative to a V
REF
envelop that has been bandwidth limited
to 200MHZ.
5. The value of V
IX
is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of
the same.
6. These charactericteristics obey the SSTL-2 class II standards.
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