參數(shù)資料
型號(hào): HDD32M72B9
廠商: Hanbit Electronics Co.,Ltd.
英文描述: DDR SDRAM Module 256Mbyte (32Mx72bit), based on32Mx8,4Banks, 8K Ref., ECC Unbuffered SO-DIMM
中文描述: 256MB的DDR SDRAM內(nèi)存模塊(32Mx72bit)根據(jù)on32Mx8,4Banks,8K的參考。,ECC無緩沖的SO - DIMM
文件頁數(shù): 5/12頁
文件大?。?/td> 210K
代理商: HDD32M72B9
HANBit
HDD32M72B9
URL : www.hbe.co.kr 5 HANBit Electronics Co.,Ltd.
REV 1.0 (July. 2003)
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
V
IN
, V
OUT
RATING
-0.5 ~ 3.6
UNTE
V
Voltage on any pin relative to Vss
Voltage on V
DD
supply relative to Vss
V
DD
-1.0 ~ 3.6
V
Voltage on V
DDQ
supply relative to Vss
V
DDQ
-0.5 ~ 3.6
V
Storage temperature
T
STG
-55 ~ +150
°
C
Power dissipation
P
D
8.0
W
Short circuit current
I
OS
50
mA
Notes :
Permanent device damage may occur if ABSOLUTE MAXIUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
POWER & DC OPERATING CONDITIONS (SSTL_2 IN/OUT)
(Recommended operating conditions (Voltage referenced to Vss = 0V, T
A
= 0 to 70
°
C) )
PARAMETER
SYMBO
L
MIN
MAX
UNIT
NOTE
Supply Voltage
V
DD
2.3
2.7
V
I/O Supply Voltage
V
DDQ
2.3
2.7
V
I/O Reference Voltage
V
REF
VDDQ/2-50mV
VDDQ/2+50mV
V
1
I/O Termination Voltage(system)
V
TT
V
REF
0.04
V
REF
+ 0.04
V
2
Input High Voltage
V
IH
(DC)
V
REF
+ 0.15
V
REF
+ 0.3
V
4
Input Low Voltage
V
IL
(DC)
-0.3
V
REF
- 0.15
V
4
Input Voltage Level, CK and /CK inputs
V
IN
(DC)
-0.3
V
DDQ
+ 0.3
V
Input Differential Voltage, CK and /CK inputs
V
ID
(DC)
0.3
V
DDQ
+ 0.6
V
3
Input leakage current
I
LI
-2
2
uA
5
Output leakage current
I
OZ
-5
5
uA
Output High current (Normal Strenth driver
(V
OUT
= V
TT
+ 0.84V)
I
OH
-16.8
mA
Output Low current (Normal Strenth driver
(V
OUT
= V
TT -
0.84V)
I
OL
16.8
Output High current (Normal Strenth driver
(V
OUT
= V
TT
+ 0.45V)
I
OH
-9
Output Low current (Normal Strenth driver
(V
OUT
= V
TT
- 0.45V)
I
OL
9
mA
Notes :
1.
Includes
±
25mV margin for DC offset on VREF, and a combined total of
±
50mV margin for all AC noise and DC offset
on VREF,bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal
DRAM noise coupled TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an
inductance of
3nH.
VTT is not applied directly to the device. V TT is a system supply for signal termination resistors, is expected to be set
equal to VREF, and must track variations in the DC level of VREF
VID is the magnitude of the difference between the input level on CK and the input level on CK.
These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in
simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to
200MHZ.
The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of
the same.
These charactericteristics obey the SSTL-2 class II standards.
2.
3.
4.
5.
6.
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