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參數(shù)資料
| 型號： | HDD32M72B9-16B |
| 廠商： | Hanbit Electronics Co.,Ltd. |
| 英文描述： | DDR SDRAM Module 256Mbyte (32Mx72bit), based on32Mx8,4Banks, 8K Ref., ECC Unbuffered SO-DIMM |
| 中文描述： | 256MB的DDR SDRAM內(nèi)存模塊（32Mx72bit）根據(jù)on32Mx8，4Banks，8K的參考。，ECC無緩沖的SO - DIMM |
| 文件頁數(shù)： | 11/12頁 |
| 文件大?。?/td> | 210K |
| 代理商： | HDD32M72B9-16B |
HANBit
HDD32M72B9
URL : www.hbe.co.kr 11 HANBit Electronics Co.,Ltd.
REV 1.0 (July. 2003)
SIMPLIFIED COMMAND TRUTH TABLE
(V=VALID, X=DON
T CARE, H=LOGIC HIGH, L=LOGIC LOW)
COMMAND
CK
E
n-1
H
H
CK
E
n
X
X
H
L
/CS
/R
A
S
L
L
/C
A
S
L
L
/WE
DM
BA
0,1
A10/
AP
A11
A9~A0
NOTE
Register
Register
Extended MRS
Mode register set
Auto refresh
L
L
L
L
X
X
OP code
OP code
1,2
1,2
3
3
3
3
Entry
H
L
L
L
H
X
X
L
H
L
H
X
L
H
X
H
H
X
H
Refresh
Self
refresh
Exit
L
H
X
X
Bank active & row addr.
Auto
disable
column
address
Auto precharge eable
Auto
disable
column
address
enable
Burst Stop
Bank selection
Precharg
e
All banks
H
X
X
V
Row address
precharge
L
4
Read &
H
X
L
H
L
H
X
V
H
Column
Address
(A0 ~A9)
4
precharge
H
L
4
Write &
Auto
precharge
H
X
L
H
L
L
X
V
H
Column
Address
(A0 ~ A9)
4,6
H
X
L
H
H
L
X
X
7
5
8
9
9
V
X
L
H
H
X
L
L
H
L
X
X
H
L
X
H
L
H
L
X
V
X
X
H
X
V
X
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
H
L
X
Clock suspend or
active power down
Exit
L
H
X
X
Entry
H
L
X
Precharge power
down mode
Exit
L
H
X
X
DM
H
V
X
H
L
X
H
X
H
X
H
No operation command
H
X
X
X
(V=Valid, X=Don't care, H=Logic high, L=Logic low)
Notes :
1. OP Code : Operand code
A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected..
6. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at t
RP
after the end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges
(Write DM latency is 0)
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
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