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參數(shù)資料
| 型號： | HDD32M72B18RWP-10A |
| 廠商： | Hanbit Electronics Co.,Ltd. |
| 英文描述： | DDR SDRAM Module 256Mbyte (32Mx72bit), based on 16Mx8, 4Banks, 4K Ref., 184Pin-DIMM with PLL & Register |
| 中文描述： | 256MB的DDR SDRAM內(nèi)存模塊（32Mx72bit），在16Mx8，4Banks，4K的參考依據(jù)。，184Pin與鎖相環(huán)內(nèi)存 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 169K |
| 代理商： | HDD32M72B18RWP-10A |
HANBit
HDD32M72B18RPW
URL : www.hbe.co.kr 7 HANBit Electronics Co.,Ltd.
REV 1.0 (August.2002)
Operating current
(burst read)
I
DD4R
BL = 2, reads, continuous burst
One bank open, Address and control inputs
changing once per clock cycle, I
OUT
= 0mA
1839
2055
2055
mA
Operating current
(Bust write)
I
DD4W
BL = 2, write, continuous burst
One bank open, Address and control inputs
changing once per clock cycle
1839
2100
2100
mA
Auto refresh current
I
DD5
tRC = tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz,
distributed refresh
2019
2415
2415
mA
Normal
336
336
336
Self
refresh
current
Low Power
I
DD6
CKE =< 0.2V, External clock should be on
tCK = 100Mhz for DDR200, 133Mhz for DDR266A
& DDR266B
318
318
318
mA
Operating current
(Four bank operation)
I
DD7A
Four bank interleaving with BL=4
-Refer to the following page for detailed test
condition
2919
3315
3315
mA
Notes:
Operation at above absolute maximum rating can adversely affect device reliability
AC OPERATING CONDITIONS
PARAMETER
STMBOL
MIN
MAX
UNIT
NOTE
Input High (Logic 1) Voltage, DQ, DQS and DM signals
V
IH
(AC)
VREF + 0.31
3
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
V
IL
(AC)
VREF - 0.31
V
3
Input Differential Voltage, CK and CK inputs
V
ID
(AC)
0.7
VDDQ+0.6
V
1
Input Crossing Point Voltage, CK and CK inputs
Notes:
1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of V
IX
is expected to equal 0.5* V
DDQ
of the transmitting device and must track variations in the DC level of
the same
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the
pad in simula-tion. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited
20MHz.
AC OPERATING TEST CONDITIONS
V
IX
(AC)
0.5*VDDQ-0.2
0.5*VDDQ+0.2
V
2
PARAMETER
VALUE
UNIT
NOTE
Input reference voltage for Clock
0.5 * V
DDQ
V
Input signal maximum peak swing
1.5
V
Input signal minimum slew rate
1.0
V
Input Levels(V
IH
/V
IL
)
V
REF
+0.35/V
REF
V
Input timing measurement reference level
V
REF
V
Output timing measurement reference level
V
TT
V
Output load condition
See Load Circuit
V
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HDD32M72D18RPW | DDR SDRAM Module 256Mbyte (32Mx72bit), based on 16Mx8, 4Banks, 4K Ref., 184Pin-DIMM with PLL & Register |
| HDD32M72B9 | DDR SDRAM Module 256Mbyte (32Mx72bit), based on32Mx8,4Banks, 8K Ref., ECC Unbuffered SO-DIMM |
| HDD32M72B9-13A | DDR SDRAM Module 256Mbyte (32Mx72bit), based on32Mx8,4Banks, 8K Ref., ECC Unbuffered SO-DIMM |
| HDD32M72B9-13B | DDR SDRAM Module 256Mbyte (32Mx72bit), based on32Mx8,4Banks, 8K Ref., ECC Unbuffered SO-DIMM |
| HDD32M72B9-16B | DDR SDRAM Module 256Mbyte (32Mx72bit), based on32Mx8,4Banks, 8K Ref., ECC Unbuffered SO-DIMM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HDD32M72B9 | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 256Mbyte (32Mx72bit), based on32Mx8,4Banks, 8K Ref., ECC Unbuffered SO-DIMM |
| HDD32M72B9-13A | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 256Mbyte (32Mx72bit), based on32Mx8,4Banks, 8K Ref., ECC Unbuffered SO-DIMM |
| HDD32M72B9-13B | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 256Mbyte (32Mx72bit), based on32Mx8,4Banks, 8K Ref., ECC Unbuffered SO-DIMM |
| HDD32M72B9-16B | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 256Mbyte (32Mx72bit), based on32Mx8,4Banks, 8K Ref., ECC Unbuffered SO-DIMM |
| HDD32M72D18RPW | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 256Mbyte (32Mx72bit), based on 16Mx8, 4Banks, 4K Ref., 184Pin-DIMM with PLL & Register |
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