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參數(shù)資料
| 型號： | HDD16M72D9W-13A |
| 廠商： | Hanbit Electronics Co.,Ltd. |
| 英文描述： | DDR SDRAM Module 128Mbyte (16Mx72bit), based on 16Mx8, 4Banks 4K Ref., 184Pin-DIMM with Unbuffered ECC |
| 中文描述： | DDR SDRAM內(nèi)存模塊128Mbyte（16Mx72bit），基于對16Mx8，4Banks 4K的參考。，184Pin，與無緩沖ECC內(nèi)存 |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 163K |
| 代理商： | HDD16M72D9W-13A |
HANBit
HDD16M72D9W
URL : www.hbe.co.kr 8 HANBit Electronics Co.,Ltd.
REV 1.0 (November.2002)
Notes :
1.
2.
Maximum burst refresh cycle : 8
The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from High_Z
to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be
High at this time, depending on t
DQSS
.
3.
The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter, but
system performance (bus turnaround) will degrade accordingly.
4.
5.
A write command can be applied with t
RCD
satisfied after this command.
For registered DIMMs, t
CL
and t
are
≥
45% of the period including both the half period jitter (t
JIT
(HP) ) of the PLL and the half
jitter due to crosstalk (t
JIT
(crosstalk) ) on the DIMM.
6.
Input Setup/Hold Slew Rate Derating
Input Setup/Hold Slew Rate
Δ
t
IS
Δ
t
IH
(V/ns)
(ps)
(ps)
0.5
0
0
0.4
+50
+50
0.3
+100
+100
-
This derating table is used to increase t
/t
in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate
based on the lesser of AC-AC slew rate and DC-DC slew rate.
7.
I/O Setup/Hold Slew Rate Derating
Input Setup/Hold Slew Rate
Δ
t
IS
Δ
t
IH
(V/ns)
(ps)
(ps)
0.5
0
0
0.4
+75
+75
0.3
+150
+150
-
This derating table is used to increase t
/t
in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate based
on the lesser of AC-AC slew rate and DC-DC slew rate.
8.
I/O Setup/Hold Plateau Derating
I/O Input Level
Δ
t
DS
Δ
t
DH
(mV)
(ps)
(ps)
±
280
+50
+50
-
This derating table is used to increase t
DS
/t
DH
in the case where the input level is flat below V
REF
±
310mV for a duration of up to 2ns.
9.
I/O Delta Rise/Fall Rate(1/slew-rate) Derating
Delta Rise/Fall Rate
Δ
t
DS
Δ
t
DH
(ns/V)
(ps)
(ps)
0
0
0
±
0.25
+50
+50
±
0.5
+100
+100
-
This derating table is used to increase t
/t
in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate is
calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall Rate =-
0/5ns/V. Input S/H slew rate based on larger of AC-AC delta rise/fall rate and DC-DC delta rise/fall rate.
10. This parameter is fir system simulation purpose. It is guranteed by design.
11. For each of the terms, if not already an integer, round to the next highest integer. t
CK
is actual to the system clock cycle time.
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參數(shù)描述 |
|---|---|
| HDD16M72D9W-13B | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 128Mbyte (16Mx72bit), based on 16Mx8, 4Banks 4K Ref., 184Pin-DIMM with Unbuffered ECC |
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