參數(shù)資料
型號(hào): HDD16M64D8W-10A
廠商: Hanbit Electronics Co.,Ltd.
英文描述: DDR SDRAM Module 128Mbyte (16Mx64bit), based on16Mx8,4Banks, 4K Ref., DIMM,
中文描述: DDR SDRAM內(nèi)存模塊128Mbyte(16Mx64bit)根據(jù)on16Mx8,4Banks,4K的參考。,內(nèi)存,
文件頁數(shù): 5/10頁
文件大小: 211K
代理商: HDD16M64D8W-10A
HANBit
HDD16M64D8W
URL : www.hbe.co.kr 5 HANBit Electronics Co.,Ltd.
REV 2.0 (November.2002)
DDR SDRAM IDD SPEC TABLE
SYMBOL
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
UNIT
NOTE
IDD0
840
760
760
mA
IDD1
1040
960
960
mA
IDD2P
28
24
24
mA
IDD2F
200
176
176
mA
IDD2Q
144
120
120
mA
IDD3P
280
280
280
mA
IDD3N
440
440
440
mA
IDD4R
1280
1136
1136
mA
IDD4W
1216
1040
1040
mA
IDD5
1480
1480
1480
mA
Normal
16
16
16
mA
IDD6
Low power
8
8
8
mA
Optional
IDD7A
2640
2400
2400
mA
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ
loading cap.
AC OPERATING CONDITIONS
PARAMETER/ CONDITION
STMBOL
MIN
MAX
UNIT
NOTE
Input High (Logic 1) Voltage, DQ, DQS and DM signals
V
IH
(AC)
V
REF
+ 0.31
3
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
V
IL
(AC)
V
REF
- 0.31
V
3
Input Differential Voltage, CK and CK inputs
V
ID
(AC)
0.7
V
DDQ
+0.6
V
1
Input Crossing Point Voltage, CK and CK inputs
Note
1. V
ID
is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of V
is expected to equal 0.5* V
of the transmitting device and must track variations in the DC level of the same.
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simulation.
the AC and DC input specificatims are refation to a V
REF
envelope that has been bandwidth limited 20MHz.
AC OPERATING TEST CONDITIONS
V
IX
(AC)
0.5*V
DDQ
-0.2
0.5*V
DDQ
+0.2
V
2
PARAMETER
VALUE
UNIT
NOTE
Input reference voltage for Clock
0.5 * V
DDQ
V
Input signal maximum peak swing
1.5
V
Input signal minimum slew rate
0.5
V/ns
Input Levels(V
IH
/V
IL
)
V
REF
+0.31/V
REF
-0.31
V
Input timing measurement reference level
V
REF
V
Output timing measurement reference level
V
TT
V
Output load condition
See Load Circuit
V
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