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參數(shù)資料
| 型號(hào)： | HD74HC76 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | Dual J-K Flip-Flops (with Preset and Clear) |
| 中文描述： | 雙JK觸發(fā)器（帶預(yù)置和清除） |
| 文件頁數(shù)： | 1/8頁 |
| 文件大小： | 54K |
| 代理商： | HD74HC76 |
HD74HC76
Dual J-K Flip-Flops (with Preset and Clear)
Description
Each flip-flop has independent J, K, preset, clear, and clock inputs and Q and
Q
outputs. This device is
edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Clear
and preset are independent of the clock and accomplished by a low logic level on the corresponding input.
Features
High Speed Operation: t
pd
(Clock to Q) = 21 ns typ (C
L
= 50 pF)
High Output Current: Fanout of 10 LSTTL Loads
Wide Operating Voltage: V
CC
= 2 to 6 V
Low Input Current: 1 μA max
Low Quiescent Supply Current: I
CC
(static) = 2 μA max (Ta = 25°C)
Function Table
Inputs
Outputs
Preset
Clear
Clock
J
K
Q
Q
L
H
X
X
X
H
L
H
L
X
X
X
L
H
L
L
X
X
X
H*
1
H*
1
H
H
L
L
No change
H
H
L
H
L
H
H
H
H
L
H
L
H
H
H
H
Toggle
H
H
L
X
X
No change
H
H
H
X
X
No change
H
H
X
X
No change
Note:
1. Q and
Q
will remain HIGH as long as Preset and Clear are Low, but Q and
Q
are unpredictable,
if Preset and Clear go HIGH simultaneously.
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