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參數(shù)資料
| 型號(hào)： | HD74HC299 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 8-bit Universal Shift/Storage Register (with 3-state outputs) |
| 中文描述： | 8位通用移位/存儲(chǔ)寄存器（3態(tài)輸出） |
| 文件頁數(shù)： | 2/11頁 |
| 文件大?。?/td> | 81K |
| 代理商： | HD74HC299 |
HD74HC299
2
Function Table
Inputs
Function
Select
Output
Control
Serial Inputs/Outputs
Outputs
Mode
Clear
S
1
S
0
G
1
G
2
Clock S
L
S
R
A/Q
A
B/Q
B
C/Q
C
D/Q
D
E/Q
E
F/Q
F
G/Q
G
H/Q
H
Q
A
’
Q
H
’
Clear
L
X
L
L
L
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
X
L
L
X
X
X
L
L
L
L
L
L
L
L
L
L
Hold
H
L
L
L
L
X
X
X
Q
A0
Q
B0
Q
C0
Q
D0
Q
E0
Q
F0
Q
G0
Q
H0
Q
A0
Q
H0
H
X
X
L
L
L
X
X
Q
A0
Q
B0
Q
C0
Q
D0
Q
E0
Q
F0
Q
G0
Q
H0
Q
A0
Q
H0
Shift
H
L
H
L
L
X
H
H
Q
An
Q
Bn
Q
Cn
Q
Dn
Q
En
Q
Fn
Q
Gn
H
Q
Gn
Right
H
L
H
L
L
X
L
L
Q
An
Q
Bn
Q
Cn
Q
Dn
Q
En
Q
Fn
Q
Gn
L
Q
Gn
Shift
H
H
L
L
L
H
X
Q
Bn
Q
Cn
Q
Dn
Q
En
Q
Fn
Q
Gn
Q
Hn
H
Q
Bn
H
Left
H
H
L
L
L
L
X
Q
Bn
Q
Cn
Q
Dn
Q
En
Q
Fn
Q
Gn
Q
Hn
L
Q
Bn
L
Load
H
H
H
X
X
X
X
a
b
c
d
e
f
g
h
a
h
Notes: 1. a to h; the level of steady-state input at inputs A through H, respectively. These data are
loaded into the flip-flop outputs are isolated from the input/output terminals.
2. Q
A0
to Q
H0
; the level of Q
through Q
, respectively, before the indicated steady-state input
conditions were established.
3. Q
An
to Q
Hn
; the level of Q
A
through Q
H
, respectively, before the most-recent
clock.
4. = ; When one or both output controls are high the eight input/output terminals are desabled to
the high-impedance state, however, sequential operation or clearing of the register is not
affected.
5. When clear is low, outputs of Q
A
’ and Q
H
’ are low, in spite of other inputs.
transition of the
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