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參數(shù)資料
| 型號(hào)： | HD74CDCF2510B |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 3.3-V Phase-lock Loop Clock Driver(3.3V鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器) |
| 中文描述： | 的3.3V鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器（3.3鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器） |
| 文件頁(yè)數(shù)： | 7/11頁(yè) |
| 文件大?。?/td> | 44K |
| 代理商： | HD74CDCF2510B |
HD74CDCF2510B
7
Switching Characteristics
(C
L
= 25 pF, Ta = 0 to 85
°
C)
Item
Symbol
V
CC
= 3.3 V
±
0.3 V
Min
Typ
Unit
From (Input)
To (Output)
Max
Phase error time
t
pe
–125
—
125
ps
CLKIN
↑
= 133 MHz
FBIN
↑
Between output pins skew
*1
t
sk (O)
—
—
150
ps
Any Y or FBOUT,
F (clkin =
133 MHz)
Any Y or
FBOUT
Cycle to cycle jitter
–75
—
75
ps
F (clkin =
133 MHz)
Any Y or
FBOUT
Duty cycle
45
—
55
%
F (clkin =
133 MHz)
Any Y or
FBOUT
Slew rate
5.0
—
1.0
volts/n
s
Any Y or
FBOUT
Analog power supply
rejection
(DC to 10 MHz)
Notes:
Vapsr
*2
100
—
—
mV
P–P
AV
CC
The specifications for parameters in this table are applicable only after any appropriate
stabilization time has elapsed.
1. The t
sk(O)
specification is only valid for equal loading of all outputs.
2. This parameter is characterized but not tested.
Timing requirements
Item
Symbol Min
Max
Unit
Test Conditions
Input clock frequency
f
clock
50
140
MHz
Input clock duty cycle
40
60
%
Stabilization time
*1
Note:
1. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its
reference signal. In order for phase lock to be obtained, a fixed-frequency, fixed-phase
reference signal must be present at CLK. Until phase lock is obtained, the specifications for
propagation delay and skew parameters given in the switching characteristics table are not
applicable.
—
1
ms
After power up
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