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參數(shù)資料
| 型號(hào)： | HD74CDC2509B |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 3.3-V Phase-lock Loop Clock Driver(3.3-V 鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器) |
| 中文描述： | 的3.3V鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器（3.3 V的鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器） |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 42K |
| 代理商： | HD74CDC2509B |
HD74CDC2509B
5
Pin Function
Pin name
No.
Type
Description
CLK
24
I
Clock input. CLK provides the clock signal to be distributed by the
HD74CDC2509B clock driver. CLK is used to provide the
reference signal to the integrated PLL that generates the clock
output signals. CLK must have a fixed frequency and fixed phase
for the PLL to obtain phase lock. Once the circuit is powered up
and a valid CLK signal is applied, a stabilization time is required for
the PLL to phase lock the feedback signal to its reference signal.
FBIN
13
I
Feedback input. FBIN provides the feedback signal to the internal
PLL. FBIN must be hard-wired to FBOUT to complete the PLL.
The integrated PLL synchronizes CLK and FBIN so that there is
nominally zero phase error between CLK and FBIN.
1G
11
I
Output bank enable. 1G is the output enable for outputs 1Y(0:4).
When 1G is low, outputs 1Y(0:4)are disabled to a logic-low state.
When 1G is high, all outputs 1Y(0:4) are enabled and switch at the
same frequency as CLK.
2G
14
I
Output bank enable. 2G is the output enable for outputs 2Y(0:3).
When 2G is low, outputs 2Y(0:3)are disabled to a logic low state.
When 2G is high, all outputs 2Y(0:3) are enabled and switch at the
same frequency as CLK.
FBOUT
12
O
Feedback output. FBOUT is dedicated for external feedback. It
switches at the same frequency as CLK. When externally wired to
FBIN, FBOUT completes the feedback loop of the PLL.
1Y(0:4)
3, 4, 5, 8, 9
O
Clock outputs. These outputs provide low-skew copies of CLK.
Output bank 1Y(0:4) is enabled via the 1G input. These outputs
can be disabled to a logic low state by deasserting the 1G control
input.
2Y(0:3)
16, 17, 20,
21
O
Clock outputs. These outputs provide low-skew copies of CLK.
Output bank 2Y(0:3) is enabled via the 2G input. These outputs
can be disabled to a logic low state by deasserting the 2G control
input.
AV
CC
23
Power
Analog power supply. AV
provides the power reference for the
analog circuitry. In addition, AV
can be used to bypass the PLL
for test purposes. When AV
is strapped to ground, PLL is
bypassed and CLK is buffered directly to the device outputs.
AGND
1
Ground Analog ground. AGND provides the ground reference for the
analog circuitry.
V
CC
GND
2, 10, 15, 22 Power
Power supply
6, 7, 18,19
Ground Ground
相關(guān)PDF資料 |
PDF描述 |
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| HD74CDC2509 | 3.3-V Phase-lock Loop Clock Driver(3.3-V 鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器) |
| HD74CDC2510B | 3.3-V Phase-lock Loop Clock Driver(3.3-V 鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器) |
| HD74CDC587 | 3.3-V Phase-lock Loop Clock Driver with 3-state Outputs(3.3-V 鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器) |
| HD74CDC857 | 3.3/2.5-V Phase-lock Loop Clock Driver |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HD74CDC2509BTEL | 制造商:Renesas Electronics Corporation 功能描述:FACT - Tape and Reel |
| HD74CDC2510BTEL | 制造商:Renesas Electronics Corporation 功能描述:FACT - Tape and Reel |
| HD74CDCF2509BTEL | 制造商:Renesas Electronics Corporation 功能描述:FACT - Tape and Reel |
| HD74CDCF2510BTEL | 制造商:Renesas Electronics Corporation 功能描述:FACT - Tape and Reel |
| HD74CDCF2510BTEL-E | 制造商:Renesas Electronics Corporation 功能描述:PLL CLOCK DRIVERS - Tape and Reel |
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