參數(shù)資料
型號(hào): HD74ALVCF162834
廠商: Hitachi,Ltd.
英文描述: 18-bit Universal Bus Driver with 3-state Outputs and Inverted Latch Enable
中文描述: 18位通用總線驅(qū)動(dòng)器,三態(tài)輸出和反向鎖存使能
文件頁(yè)數(shù): 1/16頁(yè)
文件大?。?/td> 61K
代理商: HD74ALVCF162834
HD74ALVCF162834
18-bit Universal Bus Driver with 3-state Outputs
and Inverted Latch Enable
ADE-205-226E (Z)
Preliminary
6th. Edition
February 1999
Description
The HD74ALVCF162834 is an 18-bit universal bus driver designed for 2.3 V to 3.6 V V
CC
operation.
Data flow from A to Y is controlled by the output enable (
OE
). The device operates in the transparent mode
when the latch enable (
LE
) is low. When
LE
is low, the A data is latched if the clock (CLK) input is held
at a high or low logic level. If the
LE
is high, the A data is stored in the latch/flip flop on the low to high
transition of CLK. When
OE
is high, the outputs are in the high impedance state.
To ensure the high impedance state during power up or power down,
OE
should be tied to V
CC
through a
pullup registor; the minimum value of the registor is determined by the current sinking capability of the
driver.
All outputs, which are designed to sink up to 12 mA, include series resistors to reduce overshoot and
undershoot.
Features
Supports PC133 and meets “PC SDRAM registered DIMM specification, Rev. 0.9”
V
CC
= 2.3 V to 3.6 V
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25
°
C)
Typical V
OH
undershoot > 2.0 V (@V
CC
= 3.3 V, Ta = 25
°
C)
High output current
±
12 mA (@V
CC
= 3.0 V)
All outputs have series resistors, so no external resistors are required
t
pd
(CLK to Y) = 3.5 ns (Max) (@V
CC
= 3.3
±
0.3 V, Ta = 0 to 85
°
C)
相關(guān)PDF資料
PDF描述
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