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參數(shù)資料
| 型號： | HD74ACT166TVELL |
| 元件分類： | 計(jì)數(shù)移位寄存器 |
| 英文描述： | ACT SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16 |
| 封裝： | LEAD FREE, TSSOP-16 |
| 文件頁數(shù)： | 2/9頁 |
| 文件大小： | 221K |
| 代理商： | HD74ACT166TVELL |
HD74AC166/HD74ACT166
Rev.2.00, Jul.16.2004, page 2 of 8
Logic Symbol
15
PE P
0
D
S
CP
V
CC
=Pin16
GND=Pin8
P
1
P
2
P
3
P
4
P
5
P
6
P
7
1
7
6
1
2
MR
9
13
Q
7
2
3
4
5
10
11 12
14
Pin Names
CP
1
, CP
2
D
S
PE
P
to P
7
MR
Q
7
Clock Pulse Inputs (Active Rising Edge)
Serial Data Input
Parallel Enable Input (Active Low)
Parallel Data Inputs
Asynchronous Master Reset Input (Active Low)
Last Stage Output
Functional Description
Operation is synchronous (except for Master Reset) and state changes are initiated by the rising edge of either clock
input if the other clock input is Low. When one of the clock inputs is used as an active High clock inhibt, it should
attain the High state while the other clock is still in the High state following the previous operation. When the Parallel
Enable (
PE
) input is Low, data is loaded into the register from the Parallel Data (P
0
to P
7
) inputs on the next rising edge
of the clock. When
PE
is High, information is shifted from the Serial Data (D
S
) input to Q
0
and all data in the register is
shifted one bit position (i.e., Q
0
→
Q
1
, Q
1
→
Q
2
, etc.) on the rising edge of the clock.
Truth Table
Inputs
Parallel
P
0
to P
7
Internal Outputs
Q
0
Output
Q
7
MR
PE
CP
2
CP
1
D
S
Q
6
L
H
H
H
H
H
H :
L
X
X
X
L
H
H
X
X
L
L
L
L
H
X
L
X
X
X
H
L
X
X
X
a ··· h
X
X
X
L
Q
A0
a
H
L
Q
A0
L
Q
B0
b
Q
An
Q
An
Q
B0
L
Q
H0
h
Q
Gn
Q
Gn
Q
H0
High Voltage Level
Low Voltage Level
Immaterial
: Low-to-High Clock Transition
:
:
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