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參數(shù)資料
| 型號(hào)： | HD74ACT107 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | Dual JK Flip-Flop (with Separate Clear and Clock) |
| 中文描述： | 雙JK觸發(fā)器（具有獨(dú)立清晰，時(shí)鐘） |
| 文件頁數(shù)： | 1/10頁 |
| 文件大小： | 57K |
| 代理商： | HD74ACT107 |
HD74AC107/HD74ACT107
Dual JK Flip-Flop (with Separate Clear and Clock)
Description
The HD74AC107/HD74ACT107 dual JK master/slave flip-flops have a separate clock for each flip-flop.
Inputs to the master section are controlled by the clock pulse. The clock pulse also regulates the state of the
coupling transistors which connect the master and slave sections. The sequence of operation is as follows:
1) isolate slave from master; 2) enter information from J and K inputs to master; 3) disable J and K inputs;
4) transfer information from master to slave.
Features
Outputs Source/Sink 24 mA
HD74ACT107 has TTL-Compatible Inputs
Pin Arrangement
1
2
3
4
5
6
7
J
1
Q
1
Q
1
K
1
Q
2
Q
2
GND
V
CC
C
D1
CP
1
K
2
C
D2
CP
2
J
2
14
13
12
11
10
9
8
(Top view)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HD74AC107 | Dual JK Flip-Flop (with Separate Clear and Clock)(雙JK觸發(fā)器(帶獨(dú)立清除和時(shí)鐘)) |
| HD74ACT112 | Dual JK Negative Edge-Triggered Flip-Flop |
| HD74AC112 | Dual JK Negative Edge-Triggered Flip-Flop(下降沿觸發(fā)雙JK觸發(fā)器) |
| HD74ACT161 | Synchronous Presettable Binary Counter(同步預(yù)置二進(jìn)制計(jì)數(shù)器) |
| HD74ACT163 | Synchronous Presettable Binary Counter(同步預(yù)置二進(jìn)制計(jì)數(shù)器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HD74ACT107FP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:J-K-Type Flip-Flop |
| HD74ACT107P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FLIP-FLOP|DUAL|J/K TYPE|ACT-CMOS|DIP|14PIN|PLASTIC |
| HD74ACT107RP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FLIP-FLOP|DUAL|J/K TYPE|ACT-CMOS|SOP|14PIN|PLASTIC |
| HD74ACT109FP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:J-K-Type Flip-Flop |
| HD74ACT109P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:J-K-Type Flip-Flop |
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