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參數(shù)資料
| 型號(hào)： | HD74AC373 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | Octal Transparent Latch with 3-State Output |
| 中文描述： | 八路透明鎖存器與三態(tài)輸出 |
| 文件頁(yè)數(shù)： | 3/11頁(yè) |
| 文件大?。?/td> | 63K |
| 代理商： | HD74AC373 |
HD74AC373/HD74ACT373
3
Truth Table
Inputs
OE
Outputs
LE
D
n
X
O
n
Z
H
X
L
H
L
L
L
H
H
H
L
H :
L
Z
X :
O
0
:
L
X
O
0
High Voltage Level
Low Voltage Level
High Impedance
Immaterial
Previous O
0
before Low-to-High Transition of Clock
:
:
Functional Description
The HD74AC373/HD74ACT373 contains eight D-type latches with 3-state standard outputs. When the
Latch Enable (LE) input is High, data on the Dn inputs enters the latches. In this condition the latches are
transparent, i.e., a latch output will change state each time its D input changes. When LE is Low, the
latches store the information that was present on the D inputs setup time proceding the High-to-Low
transition of LE. The 3-state standard outputs are controlled by the Output Enable (
OE
) input. When
OE
is
Low, the standard outputs are in the 2-state mode. When
OE
is High, the standard outputs are in the high
impedance mode but this does not interfere with entering new data into the latches.
Logic Diagram
O
7
G
O
D
D
7
O
6
G
O
D
D
6
O
5
G
O
D
D
5
O
4
G
O
D
D
4
O
3
G
O
D
D
3
O
2
G
O
D
D
2
O
1
G
O
D
D
1
O
0
G
O
D
D
0
LE
OE
Please note that this diagram is provided only for the understanding of logic operations and should not be
used to estimate propagation delays.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HD74AC373/HD74ACT373 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述: |
| HD74AC373FP | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:8-Bit D-Type Latch |
| HD74AC373FPEL | 制造商:RENESAS 制造商全稱(chēng):Renesas Technology Corp 功能描述:Octal Transparent Latch with 3-State Output |
| HD74AC373P | 制造商:RENESAS 制造商全稱(chēng):Renesas Technology Corp 功能描述:Octal Transparent Latch with 3-State Output |
| HD74AC373RP | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:LATCH|SINGLE|8-BIT|AC-CMOS|SOP|20PIN|PLASTIC |
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