
HD66841
38
8. Fine Adjust Register (R9)
The 4-bit fine adjust register (Figure 26) adjusts the externally supplied display timing signal (DISPTMG)
to synchronize its phase with that of LCD data. The value to be written into this register depends on the
interval between the rising edge of the DISPTMG signal and the display start position. For more details,
refer to the Display Timing Signal Fine Adjustment section and Table 13. This register is invalid if the
DISPTMG signal is generated internally, that is, if either the DCK bit or the DSP bit of control register 1
(R0) is 1.
9. PLL Frequency-Division Ratio Register (R10, R11)
The 8-bit PLL frequency-dividing ratio register (Figure 27) specifies the PLL frequency-division ratio used
for generating dot clock pulses by a PLL circuit. The PLL frequency-division ratio is the ratio of the
DOTCLK signal’s frequency to the horizontal synchronization signal’s (HSYNC) frequency. The LVIC-II
generates the DOTCLK signal according to this ratio. This register is invalid if the DOTCLK signal is
supplied externally, i.e., it is valid only in the internal register programming method when the DCK bit of
control register 1 (R0) is 0.
The value to be written into this register is N
PLL
– 731, where N
PLL
is the PLL frequency-division ratio
which can be obtained from the following expression:
N
PLL
– 731 = Ncht
×
n – 731
Ncht: Total number of horizontal characters on CRT (total number of horizontal dots on CRT
×
1/n)
n:
Horizontal character pitch (number of horizontal dots making up a character)
Ncht can be also obtained from the CRT monitor specifications as follows:
Ncht = 1/n
×
(DOTCLK frequency/HSYNC frequency)